Searched refs:FSQRT (Results 1 - 25 of 29) sorted by relevance

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/freebsd-11-stable/contrib/one-true-awk/
H A Dawk.h116 #define FSQRT 2 macro
H A Dlex.c82 { "sqrt", FSQRT, BLTIN },
H A Drun.c1502 case FSQRT:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86TargetTransformInfo.cpp1997 { ISD::FSQRT, MVT::f32, 7 }, // Haswell from http://www.agner.org/
1998 { ISD::FSQRT, MVT::v4f32, 7 }, // Haswell from http://www.agner.org/
1999 { ISD::FSQRT, MVT::v8f32, 14 }, // Haswell from http://www.agner.org/
2000 { ISD::FSQRT, MVT::f64, 14 }, // Haswell from http://www.agner.org/
2001 { ISD::FSQRT, MVT::v2f64, 14 }, // Haswell from http://www.agner.org/
2002 { ISD::FSQRT, MVT::v4f64, 28 }, // Haswell from http://www.agner.org/
2034 { ISD::FSQRT, MVT::f32, 14 }, // SNB from http://www.agner.org/
2035 { ISD::FSQRT, MVT::v4f32, 14 }, // SNB from http://www.agner.org/
2036 { ISD::FSQRT, MVT::v8f32, 28 }, // SNB from http://www.agner.org/
2037 { ISD::FSQRT, MV
[all...]
H A DX86IntrinsicsInfo.h920 X86_INTRINSIC_DATA(avx512_sqrt_pd_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
921 X86_INTRINSIC_DATA(avx512_sqrt_ps_512, INTR_TYPE_1OP, ISD::FSQRT, X86ISD::FSQRT_RND),
/freebsd-11-stable/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h640 FNEG, FABS, FSQRT, FCBRT, FSIN, FCOS, FPOWI, FPOW, enumerator in enum:llvm::ISD::NodeType
H A DBasicTTIImpl.h397 TLI->isOperationLegalOrCustom(ISD::FSQRT, VT);
1220 ISDs.push_back(ISD::FSQRT);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCTargetTransformInfo.cpp312 case Intrinsic::sqrt: Opcode = ISD::FSQRT; break;
361 Opcode = ISD::FSQRT; break;
H A DPPCISelLowering.cpp314 setOperationAction(ISD::FSQRT, MVT::f64, Expand);
319 setOperationAction(ISD::FSQRT, MVT::f32, Expand);
660 setOperationAction(ISD::FSQRT, VT, Expand);
759 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
825 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
1127 setOperationAction(ISD::FSQRT, MVT::v4f64, Legal);
1130 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
1133 setOperationAction(ISD::FSQRT, MVT::v4f64, Expand);
1136 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
1203 setTargetDAGCombine(ISD::FSQRT);
[all...]
/freebsd-11-stable/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGDumper.cpp193 case ISD::FSQRT: return "fsqrt";
H A DLegalizeFloatTypes.cpp119 case ISD::FSQRT: R = SoftenFloatRes_FSQRT(N); break;
1176 case ISD::FSQRT: ExpandFloatRes_FSQRT(N, Lo, Hi); break;
2121 case ISD::FSQRT:
H A DLegalizeVectorTypes.cpp97 case ISD::FSQRT:
891 case ISD::FSQRT:
2817 case ISD::FSQRT:
H A DLegalizeVectorOps.cpp419 case ISD::FSQRT:
H A DDAGCombiner.cpp1583 case ISD::FSQRT: return visitFSQRT(N);
12782 if (N1.getOpcode() == ISD::FSQRT) {
12786 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12794 N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12803 // it's still worthwhile to get rid of the FSQRT if possible.
12806 if (N1.getOperand(0).getOpcode() == ISD::FSQRT) {
12809 } else if (N1.getOperand(1).getOpcode() == ISD::FSQRT) {
12814 // We found a FSQRT, so try to make this fold:
12866 // FSQRT nodes have flags that propagate to the created nodes.
12989 if (!DAG.getTargetLoweringInfo().isOperationLegalOrCustom(ISD::FSQRT, V
[all...]
H A DLegalizeDAG.cpp3949 case ISD::FSQRT:
4508 case ISD::FSQRT:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp1715 setOperationAction(ISD::FSQRT, MVT::f128, Legal);
1740 setOperationAction(ISD::FSQRT, MVT::f128, Custom);
1792 setOperationAction(ISD::FSQRT, MVT::f32, Promote);
3046 case ISD::FSQRT: return LowerF128Op(Op, DAG,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp151 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
395 setOperationAction(ISD::FSQRT, Ty, Legal);
1921 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp207 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp1437 {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS, ISD::FSINCOS,
1482 ISD::FREM, ISD::FNEG, ISD::FABS, ISD::FSQRT, ISD::FSIN,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp271 setOperationAction(ISD::FSQRT, MVT::f128, Expand);
446 setOperationAction(ISD::FSQRT, MVT::f16, Promote);
481 setOperationAction(ISD::FSQRT, MVT::v4f16, Expand);
495 setOperationAction(ISD::FSQRT, MVT::v8f16, Expand);
722 setOperationAction(ISD::FSQRT, MVT::v1f64, Expand);
H A DAArch64FastISel.cpp3677 unsigned ResultReg = fastEmit_r(VT, VT, ISD::FSQRT, Op0Reg, Op0IsKill);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp504 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
536 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp572 for (const auto &Op : {ISD::FDIV, ISD::FREM, ISD::FSQRT, ISD::FSIN, ISD::FCOS,
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.cpp7569 if (RHS.getOpcode() == ISD::FSQRT)
8606 case ISD::FSQRT:
8768 case ISD::FSQRT:
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp348 setOperationAction(ISD::FSQRT, VT, Expand);
797 setOperationAction(ISD::FSQRT, MVT::v2f64, Expand);
818 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
834 setOperationAction(ISD::FSQRT, MVT::v2f32, Expand);
963 setOperationAction(ISD::FSQRT, MVT::f64, Expand);

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