/linux-master/drivers/gpu/drm/xe/ |
H A D | xe_guc_hxg_helpers.h | 73 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 74 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_SUCCESS) | 75 FIELD_PREP(GUC_HXG_RESPONSE_MSG_0_DATA0, data0); 82 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 83 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_RESPONSE_FAILURE) | 84 FIELD_PREP(GUC_HXG_FAILURE_MSG_0_HINT, hint) | 85 FIELD_PREP(GUC_HXG_FAILURE_MSG_0_ERROR, error); 92 msg[0] = FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 93 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_NO_RESPONSE_BUSY) | 94 FIELD_PREP(GUC_HXG_BUSY_MSG_0_COUNTE [all...] |
/linux-master/drivers/accel/habanalabs/include/gaudi/ |
H A D | gaudi_masks.h | 15 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MASK, 0xF)) | \ 16 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CQF_EN_MASK, 0xF)) | \ 17 (FIELD_PREP(DMA0_QM_GLBL_CFG0_CP_EN_MASK, 0xF))) 20 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ 21 (FIELD_PREP(DMA0_QM_GLBL_PROT_CQF_MASK, 0xF)) | \ 22 (FIELD_PREP(DMA0_QM_GLBL_PROT_CP_MASK, 0xF)) | \ 23 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) 26 (FIELD_PREP(DMA0_QM_GLBL_PROT_PQF_MASK, 0xF)) | \ 27 (FIELD_PREP(DMA0_QM_GLBL_PROT_ERR_MASK, 0x1))) 30 (FIELD_PREP(DMA0_QM_GLBL_CFG0_PQF_EN_MAS [all...] |
/linux-master/drivers/net/ethernet/mellanox/mlxbf_gige/ |
H A D | mlxbf_gige_mdio_bf2.h | 47 #define MLXBF2_GIGE_MDIO_CFG_VAL (FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_MODE_MASK, 1) | \ 48 FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO3_3_MASK, 1) | \ 49 FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_FULL_DRIVE_MASK, 1) | \ 50 FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_IN_SAMP_MASK, 6) | \ 51 FIELD_PREP(MLXBF2_GIGE_MDIO_CFG_MDIO_OUT_SAMP_MASK, 13))
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/linux-master/drivers/net/wireless/ath/ath11k/ |
H A D | hal_tx.c | 43 FIELD_PREP(BUFFER_ADDR_INFO0_ADDR, ti->paddr); 45 FIELD_PREP(BUFFER_ADDR_INFO1_ADDR, 48 FIELD_PREP(BUFFER_ADDR_INFO1_RET_BUF_MGR, ti->rbm_id) | 49 FIELD_PREP(BUFFER_ADDR_INFO1_SW_COOKIE, ti->desc_id); 52 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_DESC_TYPE, ti->type) | 53 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCAP_TYPE, ti->encap_type) | 54 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ENCRYPT_TYPE, 56 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_SEARCH_TYPE, 58 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_ADDR_EN, 60 FIELD_PREP(HAL_TCL_DATA_CMD_INFO0_CMD_NU [all...] |
/linux-master/drivers/infiniband/hw/irdma/ |
H A D | uda.c | 31 qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | 32 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | 33 FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); 35 qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) | 36 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) | 37 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | 38 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16); 42 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | 43 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); 45 FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR [all...] |
/linux-master/drivers/iio/adc/ |
H A D | stm32-dfsdm.h | 52 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v) 54 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v) 56 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v) 58 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v) 60 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v) 62 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v) 64 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v) 66 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v) 68 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v) 70 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MAS [all...] |
/linux-master/drivers/tty/serial/ |
H A D | atmel_serial.h | 44 #define ATMEL_US_USMODE_NORMAL FIELD_PREP(ATMEL_US_USMODE, 0) 45 #define ATMEL_US_USMODE_RS485 FIELD_PREP(ATMEL_US_USMODE, 1) 46 #define ATMEL_US_USMODE_HWHS FIELD_PREP(ATMEL_US_USMODE, 2) 47 #define ATMEL_US_USMODE_MODEM FIELD_PREP(ATMEL_US_USMODE, 3) 48 #define ATMEL_US_USMODE_ISO7816_T0 FIELD_PREP(ATMEL_US_USMODE, 4) 49 #define ATMEL_US_USMODE_ISO7816_T1 FIELD_PREP(ATMEL_US_USMODE, 6) 50 #define ATMEL_US_USMODE_IRDA FIELD_PREP(ATMEL_US_USMODE, 8) 52 #define ATMEL_US_USCLKS_MCK FIELD_PREP(ATMEL_US_USCLKS, 0) 53 #define ATMEL_US_USCLKS_MCK_DIV8 FIELD_PREP(ATMEL_US_USCLKS, 1) 54 #define ATMEL_US_USCLKS_GCLK FIELD_PREP(ATMEL_US_USCLK [all...] |
/linux-master/drivers/net/ethernet/microchip/lan966x/ |
H A D | lan966x_regs.h | 39 FIELD_PREP(AFI_PORT_FRM_OUT_FRM_OUT_CNT, x) 48 FIELD_PREP(AFI_PORT_CFG_FC_SKIP_TTI_INJ, x) 54 FIELD_PREP(AFI_PORT_CFG_FRM_OUT_MAX, x) 63 FIELD_PREP(ANA_ADVLEARN_VLAN_CHK, x) 75 FIELD_PREP(ANA_ANAINTR_INTR, x) 81 FIELD_PREP(ANA_ANAINTR_INTR_ENA, x) 90 FIELD_PREP(ANA_AUTOAGE_AGE_PERIOD, x) 99 FIELD_PREP(ANA_MIRRORPORTS_MIRRORPORTS, x) 108 FIELD_PREP(ANA_EMIRRORPORTS_EMIRRORPORTS, x) 117 FIELD_PREP(ANA_FLOODING_FLD_UNICAS [all...] |
/linux-master/drivers/net/ethernet/microchip/sparx5/ |
H A D | sparx5_main_regs.h | 66 FIELD_PREP(ANA_AC_RAM_INIT_RAM_INIT, x) 72 FIELD_PREP(ANA_AC_RAM_INIT_RAM_CFG_HOOK, x) 82 FIELD_PREP(ANA_AC_OWN_UPSID_OWN_UPSID, x) 100 FIELD_PREP(ANA_AC_SRC_CFG2_PORT_MASK2, x) 118 FIELD_PREP(ANA_AC_PGID_CFG2_PORT_MASK2, x) 128 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_QU, x) 134 FIELD_PREP(ANA_AC_PGID_MISC_CFG_STACK_TYPE_ENA, x) 140 FIELD_PREP(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA, x) 150 FIELD_PREP(ANA_AC_TSN_SF_TSN_STREAM_BLOCK_OVERSIZE_STICKY, x) 156 FIELD_PREP(ANA_AC_TSN_SF_PORT_NU [all...] |
/linux-master/drivers/phy/amlogic/ |
H A D | phy-meson-g12a-usb2.c | 193 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | 194 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | 196 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | 202 FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | 203 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | 204 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | 205 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | 206 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); 208 value = FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | 209 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_ [all...] |
/linux-master/drivers/phy/microchip/ |
H A D | lan966x_serdes_regs.h | 22 FIELD_PREP(HSIO_SD_CFG_PHY_RESET, x) 28 FIELD_PREP(HSIO_SD_CFG_TX_RESET, x) 34 FIELD_PREP(HSIO_SD_CFG_TX_RATE, x) 40 FIELD_PREP(HSIO_SD_CFG_TX_INVERT, x) 46 FIELD_PREP(HSIO_SD_CFG_TX_EN, x) 52 FIELD_PREP(HSIO_SD_CFG_TX_DATA_EN, x) 58 FIELD_PREP(HSIO_SD_CFG_TX_CM_EN, x) 64 FIELD_PREP(HSIO_SD_CFG_LANE_10BIT_SEL, x) 70 FIELD_PREP(HSIO_SD_CFG_RX_TERM_EN, x) 76 FIELD_PREP(HSIO_SD_CFG_RX_RESE [all...] |
H A D | sparx5_serdes_regs.h | 36 FIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x) 42 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x) 48 FIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x) 57 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x) 63 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x) 69 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x) 75 FIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x) 81 FIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x) 90 FIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x) 99 FIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_ [all...] |
/linux-master/drivers/net/can/spi/mcp251xfd/ |
H A D | mcp251xfd-chip-fifo.c | 31 fifo_con = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK, 38 fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 41 fifo_con |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 71 val = FIELD_PREP(MCP251XFD_REG_TEFCON_FSIZE_MASK, 82 val = FIELD_PREP(MCP251XFD_REG_FIFOCON_FSIZE_MASK, 88 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 91 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_PLSIZE_MASK, 95 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK, 98 val |= FIELD_PREP(MCP251XFD_REG_FIFOCON_TXAT_MASK,
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/linux-master/drivers/i3c/master/mipi-i3c-hci/ |
H A D | cmd_v1.c | 23 #define CMD_0_ATTR_A FIELD_PREP(CMD_0_ATTR, 0x2) 27 #define CMD_A0_DEV_COUNT(v) FIELD_PREP(W0_MASK(29, 26), v) 28 #define CMD_A0_DEV_INDEX(v) FIELD_PREP(W0_MASK(20, 16), v) 29 #define CMD_A0_CMD(v) FIELD_PREP(W0_MASK(14, 7), v) 30 #define CMD_A0_TID(v) FIELD_PREP(W0_MASK( 6, 3), v) 36 #define CMD_0_ATTR_I FIELD_PREP(CMD_0_ATTR, 0x1) 38 #define CMD_I1_DATA_BYTE_4(v) FIELD_PREP(W1_MASK(63, 56), v) 39 #define CMD_I1_DATA_BYTE_3(v) FIELD_PREP(W1_MASK(55, 48), v) 40 #define CMD_I1_DATA_BYTE_2(v) FIELD_PREP(W1_MASK(47, 40), v) 41 #define CMD_I1_DATA_BYTE_1(v) FIELD_PREP(W1_MAS [all...] |
H A D | cmd_v2.c | 24 #define CMD_0_ATTR_U FIELD_PREP(CMD_0_ATTR, 0x4) 26 #define CMD_U3_HDR_TSP_ML_CTRL(v) FIELD_PREP(W3_MASK(107, 104), v) 27 #define CMD_U3_IDB4(v) FIELD_PREP(W3_MASK(103, 96), v) 28 #define CMD_U3_HDR_CMD(v) FIELD_PREP(W3_MASK(103, 96), v) 29 #define CMD_U2_IDB3(v) FIELD_PREP(W2_MASK( 95, 88), v) 30 #define CMD_U2_HDR_BT(v) FIELD_PREP(W2_MASK( 95, 88), v) 31 #define CMD_U2_IDB2(v) FIELD_PREP(W2_MASK( 87, 80), v) 32 #define CMD_U2_BT_CMD2(v) FIELD_PREP(W2_MASK( 87, 80), v) 33 #define CMD_U2_IDB1(v) FIELD_PREP(W2_MASK( 79, 72), v) 34 #define CMD_U2_BT_CMD1(v) FIELD_PREP(W2_MAS [all...] |
/linux-master/drivers/net/ethernet/sunplus/ |
H A D | spl2sw_phy.c | 24 reg |= FIELD_PREP(MAC_FORCE_RMII_LINK, mac->lan_port); 27 reg |= FIELD_PREP(MAC_FORCE_RMII_SPD, mac->lan_port); 29 reg &= FIELD_PREP(MAC_FORCE_RMII_SPD, ~mac->lan_port) | 34 reg |= FIELD_PREP(MAC_FORCE_RMII_DPX, mac->lan_port); 36 reg &= FIELD_PREP(MAC_FORCE_RMII_DPX, ~mac->lan_port) | 41 reg |= FIELD_PREP(MAC_FORCE_RMII_FC, mac->lan_port); 43 reg &= FIELD_PREP(MAC_FORCE_RMII_FC, ~mac->lan_port) | 47 reg &= FIELD_PREP(MAC_FORCE_RMII_LINK, ~mac->lan_port) |
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/linux-master/drivers/hwtracing/coresight/ |
H A D | ultrasoc-smb.h | 32 #define SMB_GLB_CFG_DEFAULT (FIELD_PREP(SMB_GLB_CFG_BURST_LEN_MSK, 0xf) | \ 33 FIELD_PREP(SMB_GLB_CFG_IDLE_PRD_MSK, 0xf) | \ 34 FIELD_PREP(SMB_GLB_CFG_MEM_WR_MSK, 0x3) | \ 35 FIELD_PREP(SMB_GLB_CFG_MEM_RD_MSK, 0x1b)) 54 FIELD_PREP(SMB_LB_CFG_LO_FLOW_MSK, 0xf)) 58 #define SMB_LB_CFG_HI_DEFAULT FIELD_PREP(SMB_LB_CFG_HI_RANGE_UP_MSK, 0xff) 73 FIELD_PREP(SMB_LB_INT_CTRL_BUF_NOTE_MSK, 0xf)) 78 #define SMB_LB_INT_STS_RESET FIELD_PREP(SMB_LB_INT_STS_BUF_RESET_MSK, 0xf)
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/linux-master/arch/arm64/kvm/hyp/include/nvhe/ |
H A D | fixed_config.h | 55 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL0), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ 56 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL1), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ 57 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL2), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ 58 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_EL3), ID_AA64PFR0_EL1_ELx_64BIT_ONLY) | \ 59 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64PFR0_EL1_RAS), ID_AA64PFR0_EL1_RAS_IMP) \ 94 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \ 95 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASIDBITS), ID_AA64MMFR0_EL1_ASIDBITS_16) \ 189 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA), ID_AA64ISAR1_EL1_APA_PAuth) | \ 190 FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API), ID_AA64ISAR1_EL1_API_PAuth) \ 194 FIELD_PREP(ARM64_FEATURE_MAS [all...] |
/linux-master/drivers/crypto/ccree/ |
H A D | cc_hw_queue_defs.h | 224 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); 242 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, upper_32_bits(addr)); 244 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | 245 FIELD_PREP(WORD1_DIN_SIZE, size) | 246 FIELD_PREP(WORD1_NS_BIT, axi_sec); 260 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); 273 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); 274 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); 276 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); 291 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZ [all...] |
/linux-master/include/linux/mfd/ |
H A D | ti_am335x_tscadc.h | 55 #define STEPCONFIG_MODE(val) FIELD_PREP(GENMASK(1, 0), (val)) 58 #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val)) 66 #define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val)) 68 #define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val)) 70 #define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val)) 74 #define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val)) 78 #define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val)) 81 #define STEPDELAY_SAMPLE(val) FIELD_PREP(GENMASK(31, 24), (val)) 86 #define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val)) 88 #define STEPCHARGE_INM(val) FIELD_PREP(GENMAS [all...] |
/linux-master/drivers/net/ethernet/marvell/prestera/ |
H A D | prestera_dsa.c | 67 dsa->vlan.vid |= FIELD_PREP(PRESTERA_DSA_VID, field); 72 dsa->hw_dev_num |= FIELD_PREP(PRESTERA_DSA_DEV_NUM, field); 89 words[0] |= FIELD_PREP(PRESTERA_DSA_W0_CMD, PRESTERA_DSA_CMD_FROM_CPU); 91 words[0] |= FIELD_PREP(PRESTERA_DSA_W0_DEV_NUM, dev_num); 93 words[3] |= FIELD_PREP(PRESTERA_DSA_W3_DEV_NUM, dev_num); 95 words[3] |= FIELD_PREP(PRESTERA_DSA_W3_DST_EPORT, dsa->port_num); 97 words[0] |= FIELD_PREP(PRESTERA_DSA_W0_EXT_BIT, 1); 98 words[1] |= FIELD_PREP(PRESTERA_DSA_W1_EXT_BIT, 1); 99 words[2] |= FIELD_PREP(PRESTERA_DSA_W2_EXT_BIT, 1);
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/linux-master/drivers/net/wireless/mediatek/mt76/mt76x2/ |
H A D | usb_phy.c | 64 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | 65 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | 66 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | 67 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | 68 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), 69 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | 70 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | 71 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | 72 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | 73 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MAS [all...] |
/linux-master/drivers/net/phy/qcom/ |
H A D | qcom.h | 111 #define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0) 112 #define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1) 113 #define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2) 114 #define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3) 115 #define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4) 116 #define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5) 117 #define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6) 118 #define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7) 120 #define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0) 121 #define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MAS [all...] |
/linux-master/drivers/net/ethernet/stmicro/stmmac/ |
H A D | dwmac-mediatek.c | 201 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); 202 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); 203 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); 205 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); 206 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); 207 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); 216 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); 217 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->rx_delay); 218 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->rx_inv); 220 delay_val |= FIELD_PREP(ETH_DLY_GTXC_ENABL [all...] |
/linux-master/drivers/bus/mhi/ |
H A D | common.h | 121 #define MHI_TRE_CMD_NOOP_DWORD1 cpu_to_le32(FIELD_PREP(GENMASK(23, 16), MHI_CMD_NOP)) 126 #define MHI_TRE_CMD_RESET_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ 127 FIELD_PREP(GENMASK(23, 16), \ 133 #define MHI_TRE_CMD_STOP_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ 134 FIELD_PREP(GENMASK(23, 16), \ 140 #define MHI_TRE_CMD_START_DWORD1(chid) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), chid) | \ 141 FIELD_PREP(GENMASK(23, 16), \ 150 #define MHI_TRE_EV_DWORD0(code, len) cpu_to_le32(FIELD_PREP(GENMASK(31, 24), code) | \ 151 FIELD_PREP(GENMASK(15, 0), len)) 152 #define MHI_TRE_EV_DWORD1(chid, type) cpu_to_le32(FIELD_PREP(GENMAS [all...] |