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f2a77dd6 |
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14-Feb-2023 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Updated register interface with VCAP ES0 access This provides access to the ES0 VCAP register targets Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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edad83e2 |
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02-Feb-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: add registers needed for PSFP Add registers needed for PSFP. This patch also renames a single register, shortening its name (SYS_CLK_PER_100PS). Uses have been update accordingly. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Reviewed-by: Simon Horman <simon.horman@corigine.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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9d712b8d |
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27-Jan-2023 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Add ES2 VCAP model and updated KUNIT VCAP model This provides the VCAP model for the Sparx5 ES2 (Egress Stage 2) VCAP. This VCAP provides tagging and remarking functionality This also renames a VCAP keyfield: VCAP_KF_MIRROR_ENA becomes VCAP_KF_MIRROR_PROBE, as the first name was caused by a mistake in the model transformation. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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545609fd |
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24-Jan-2023 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Add IS0 VCAP keyset configuration for Sparx5 This adds the IS0 VCAP port keyset configuration for Sparx5 and also updates the debugFS support to show the keyset configuration. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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246c77f6 |
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18-Jan-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for DSCP rewrite Add support for DSCP rewrite in Sparx5 driver. On egress DSCP is rewritten from either classified DSCP, or frame DSCP. Classified DSCP is determined by the Analyzer Classifier on ingress, and is mapped from classified QoS class and DP level. Classification of DSCP is by default enabled for all ports. It is required that DSCP is trusted for the egress port *and* rewrite table is not empty, in order to rewrite DSCP based on classified DSCP, otherwise DSCP is always rewritten from frame DSCP. classified_dscp = qos_dscp_map[8 * dp_level + qos_class]; if (active_mappings && dscp_is_trusted) rewritten_dscp = classified_dscp else rewritten_dscp = frame_dscp To rewrite DSCP to 20 for any frames with priority 7: $ dcb apptrust set dev eth0 order dscp $ dcb rewr add dev eth0 7:20 <-- not in iproute2/dcb yet Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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2234879f |
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18-Jan-2023 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for PCP rewrite Add support for rewrite of PCP and DEI, based on classified Quality of Service (QoS) class and Drop-Precedence (DP) level. The DCB rewrite table is queried for mappings between priority and PCP/DEI. The classified DP level is then encoded in the DEI bit, if a mapping for DEI exists. Sparx5 has four DP levels, where by default, 0 is mapped to DE0 and 1-3 are mapped to DE1. If a mapping exists where DEI=1, then all classified DP levels mapped to DE1 will set the DEI bit. The other way around for DEI=0. Effectively, this means that the tagged DEI bit will reflect the DP level for any mappings where DEI=1. Map priority=1 to PCP=1 and DEI=1: $ dcb rewr add dev eth0 pcp-prio 1:1de Map priority=7 to PCP=2 and DEI=0 $ dcb rewr add dev eth0 pcp-prio 7:2nd Also, sparx5_dcb_ieee_dscp_setdel() has been refactored, to work for both APP and rewrite entries. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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92ef3d01 |
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01-Nov-2022 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for offloading pcp table Add new registers and functions to support offload of pcp app entries. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Paolo Abeni <pabeni@redhat.com>
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45c00ad0 |
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20-Oct-2022 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: microchip: sparx5: Adding IS2 VCAP register interface This adds the register interface needed to access the Sparx5 Ingress Stage 2 VCAP (IS2). The Sparx5 Chip Register Model can be browsed at this location: https://github.com/microchip-ung/sparx-5_reginfo Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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21122542 |
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19-Sep-2022 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for offloading ets qdisc Add support for offloading ets qdisc to sparx5 switch. The ets qdisc makes it possible to configure a mix og strict and bandwidth-sharing bands. The ets qdisc must be attached as a root qdisc. Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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e02a5ac6 |
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19-Sep-2022 |
Daniel Machon <daniel.machon@microchip.com> |
net: microchip: sparx5: add support for offloading tbf qdisc Add support for offloading tbf qdisc to sparx5 qdisc. The tbf qdisc makes it possible to attach a shaper on traffic egressing from a port or a queue. Per-port tbf qdiscs are attached as a root qdisc directly and queue tbf qdiscs are attached to one of the classes of a parent qdisc (such as mqprio). Signed-off-by: Daniel Machon <daniel.machon@microchip.com> Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3193a611 |
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03-Mar-2022 |
Horatiu Vultur <horatiu.vultur@microchip.com> |
net: sparx5: Add registers that are used by ptp functionality Add the registers that will be used to configure the PHC in the HW. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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3cfa11ba |
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24-Jun-2021 |
Steen Hegelund <steen.hegelund@microchip.com> |
net: sparx5: add the basic sparx5 driver This adds the Sparx5 basic SwitchDev driver framework with IO range mapping, switch device detection and core clock configuration. Support for ports, phylink, netdev, mactable etc. are in the following patches. Signed-off-by: Steen Hegelund <steen.hegelund@microchip.com> Signed-off-by: Bjarni Jonasson <bjarni.jonasson@microchip.com> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net>
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