| /linux-master/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_dio_stream_encoder.c | 312 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
322 REG_UPDATE_2(DP_VID_TIMING,
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dio_stream_encoder.c | 321 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
331 REG_UPDATE_2(DP_VID_TIMING,
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| H A D | dcn314_dio_stream_encoder.h | 97 SRI(DP_VID_TIMING, DP, id), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn35/ |
| H A D | dcn35_dio_stream_encoder.c | 344 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
354 REG_UPDATE_2(DP_VID_TIMING,
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| H A D | dcn35_dio_stream_encoder.h | 95 SRI(DP_VID_TIMING, DP, id), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_stream_encoder.c | 499 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
509 REG_UPDATE_2(DP_VID_TIMING,
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| /linux-master/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_stream_encoder.h | 92 SRI(DP_VID_TIMING, DP, id), \
166 SE_SF(DP_VID_TIMING, DP_VID_M_N_GEN_EN, mask_sh),\
312 SE_SF(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, mask_sh)
664 uint32_t DP_VID_TIMING; member in struct:dce110_stream_enc_registers
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| H A D | dce_stream_encoder.c | 322 REG_UPDATE(DP_VID_TIMING, DP_VID_M_DOUBLE_VALUE_EN, 1);
325 REG_UPDATE(DP_VID_TIMING, DP_VID_N_MUL, 1);
976 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
986 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 1);
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn35/ |
| H A D | dcn35_resource.h | 127 SRI_ARR(DP_VID_TIMING, DP, id), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_stream_encoder.c | 990 REG_UPDATE(DP_VID_TIMING, DP_VID_M_N_GEN_EN, 0);
1000 REG_UPDATE_2(DP_VID_TIMING,
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| H A D | dcn10_stream_encoder.h | 94 SRI(DP_VID_TIMING, DP, id), \
143 uint32_t DP_VID_TIMING; member in struct:dcn10_stream_enc_registers
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| /linux-master/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_dio_stream_encoder.h | 96 SRI(DP_VID_TIMING, DP, id), \
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn32/ |
| H A D | dcn32_resource.h | 295 SRI_ARR(DP_VID_TIMING, DP, id), SRI_ARR(DP_SEC_AUD_N, DP, id), \
|