Searched refs:DMA_ENABLE (Results 1 - 12 of 12) sorted by relevance

/linux-master/arch/m68k/include/asm/
H A Ddvma.h161 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ macro
206 #define DMA_OFF(regs) ((((regs)->cond_reg) &= (~DMA_ENABLE)))
212 ((((regs)->cond_reg |= (DMA_ST_WRITE|DMA_ENABLE|DMA_INT_ENAB))))
214 ((((regs)->cond_reg |= ((DMA_ENABLE|DMA_INT_ENAB)&(~DMA_ST_WRITE)))))
/linux-master/arch/sparc/include/asm/
H A Ddma.h43 #define DMA_ENABLE 0x00000200 /* Fire up DMA, handle requests */ macro
/linux-master/drivers/scsi/
H A Dsun3x_esp.c121 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
138 csr |= DMA_ENABLE;
H A Dsun_esp.c252 esp->prev_hme_dmacsr &= ~(DMA_ENABLE | DMA_ST_WRITE |
355 ~(DMA_ST_WRITE | DMA_ENABLE));
378 val &= ~(DMA_ENABLE | DMA_ST_WRITE | DMA_BCNT_ENAB);
402 csr |= DMA_SCSI_DISAB | DMA_ENABLE;
414 csr |= DMA_ENABLE;
/linux-master/drivers/soc/ti/
H A Dknav_dma.c25 #define DMA_ENABLE BIT(31) macro
156 writel_relaxed(DMA_ENABLE, &chan->reg_chan->control);
216 if ((value & DMA_ENABLE) == 0)
220 if (readl_relaxed(&chan->reg_chan->control) & DMA_ENABLE) {
262 writel_relaxed(DMA_ENABLE, &dma->reg_tx_chan[i].control);
287 writel_relaxed(DMA_ENABLE, &dma->reg_rx_chan[i].control);
301 v = ~DMA_ENABLE & REG_MASK;
/linux-master/drivers/spi/
H A Dspi-qcom-qspi.c28 #define DMA_ENABLE BIT(8) macro
451 if (!(mstr_cfg & DMA_ENABLE)) {
452 mstr_cfg |= DMA_ENABLE;
468 if (mstr_cfg & DMA_ENABLE) {
469 mstr_cfg &= ~DMA_ENABLE;
506 mstr_cfg &= ~DMA_ENABLE;
/linux-master/include/linux/usb/
H A Dnet2280.h338 #define DMA_ENABLE 1 macro
/linux-master/drivers/mtd/nand/raw/
H A Ddenali.h267 #define DMA_ENABLE 0x700 macro
H A Ddenali.c683 iowrite32(DMA_ENABLE__FLAG, denali->reg + DMA_ENABLE);
689 ioread32(denali->reg + DMA_ENABLE);
700 iowrite32(0, denali->reg + DMA_ENABLE);
/linux-master/drivers/net/ethernet/cirrus/
H A Dcs89x0.h421 #define DMA_ENABLE 0x00 /* Enable channel n */ macro
/linux-master/drivers/usb/gadget/udc/
H A Dnet2272.h389 #define DMA_ENABLE 0 macro
H A Dnet2280.c834 BIT(DMA_ENABLE);
838 handshake(&dma->dmactl, BIT(DMA_ENABLE), 0, 50);
843 writel(readl(&dma->dmactl) & ~BIT(DMA_ENABLE), &dma->dmactl);
877 WARN_ON(readl(&dma->dmactl) & BIT(DMA_ENABLE));
901 writel(BIT(DMA_ENABLE), &dma->dmactl);

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