Searched refs:DMA0_REGISTER_OFFSET (Results 1 - 10 of 10) sorted by relevance
| /linux-master/drivers/gpu/drm/radeon/ |
| H A D | ni_dma.c | 61 reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET;
85 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
106 reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET;
165 rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
167 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl);
197 reg_offset = DMA0_REGISTER_OFFSET;
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| H A D | ni.c | 844 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
1106 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
1743 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
1824 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
1826 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
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| H A D | si.c | 1297 case (DMA_STATUS_REG + DMA0_REGISTER_OFFSET):
3258 WREG32(DMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
3782 tmp = RREG32(DMA_STATUS_REG + DMA0_REGISTER_OFFSET);
3864 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
3866 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
4031 tmp = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET);
4033 WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, tmp);
5519 offset = DMA0_REGISTER_OFFSET;
5531 offset = DMA0_REGISTER_OFFSET;
5938 tmp = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET)
[all...] |
| H A D | nid.h | 1301 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| H A D | sid.h | 1812 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | si_dma.c | 32 DMA0_REGISTER_OFFSET,
591 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
593 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
596 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET);
598 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl);
650 offset = DMA0_REGISTER_OFFSET;
662 offset = DMA0_REGISTER_OFFSET;
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| H A D | si_enums.h | 131 #define DMA0_REGISTER_OFFSET 0x000 macro
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| H A D | sid.h | 1875 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ macro
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| H A D | si.c | 1119 {DMA_STATUS_REG + DMA0_REGISTER_OFFSET},
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| H A D | gfx_v6_0.c | 1702 WREG32(mmDMA_TILING_CONFIG + DMA0_REGISTER_OFFSET, gb_addr_config);
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