| /linux-master/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; local
80 DLL = !ram->next->bios.ramcfg_DLLoff;
89 DLL = !(ram->mr[1] & 0x1);
117 ram->mr[1] |= !DLL << 6;
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| H A D | sddr2.c | 63 int CL, WR, DLL = 0, ODT = 0; local
69 DLL = !ram->next->bios.ramcfg_DLLoff;
98 ram->mr[1] |= !DLL;
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| H A D | sddr3.c | 72 int CWL, CL, WR, DLL = 0, ODT = 0; local
74 DLL = !ram->next->bios.ramcfg_DLLoff;
115 ram->mr[1] |= !DLL;
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| /linux-master/arch/x86/boot/ |
| H A D | early_serial_console.c | 21 #define DLL 0 /* Divisor Latch Low */ macro
39 outb(divisor & 0xff, port + DLL);
109 dll = inb(port + DLL);
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| /linux-master/arch/arm/mach-omap2/ |
| H A D | sleep24xx.S | 31 * R0 : DLL ctrl value pre-Sleep
36 * when we get called, but the DLL probably isn't. We will wait a bit more in
37 * case the DPLL isn't quite there yet. The code will wait on DLL for DDR even
48 * The DLL load value is not kept in RETENTION or OFF. It needs to be restored
60 mov r5, #0x2000 @ set delay (DPLL relock + DLL relock)
76 strne r0, [r1] @ rewrite DLLA to force DLL reload
78 strne r0, [r1] @ rewrite DLLB to force DLL reload
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| H A D | sram242x.S | 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
228 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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| H A D | sram243x.S | 52 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
84 /* ensure the DLL has relocked */
86 mov r4, #0x800 @ delay DLL relock, min 0x400 L3 clocks
172 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
173 bne freq_out @ leave if SDR, no DLL function
175 /* With DDR, we need to take care of the DLL for the frequency change */
180 mov r1, #0x2000 @ wait DLL relock, min 0x400 L3 clocks
228 * Set dividers and pll. Also recalculate DLL value for DDR and unlock mode.
291 orr r10, r10, #0x8 @ make sure DLL on (es2 bit pos)
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| /linux-master/arch/arm/mach-orion5x/ |
| H A D | tsx09-common.c | 33 writel(divisor & 0xff, UART1_REG(DLL));
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| H A D | terastation_pro2-setup.c | 276 writel(divisor & 0xff, UART1_REG(DLL));
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| H A D | kurobox_pro-setup.c | 298 writel(divisor & 0xff, UART1_REG(DLL));
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| /linux-master/drivers/power/reset/ |
| H A D | qnap-poweroff.c | 61 writel(divisor & 0xff, UART1_REG(DLL));
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| /linux-master/drivers/usb/serial/ |
| H A D | io_16654.h | 40 #define DLL 8 // Bank2[ 0 ] Divisor Latch LSB macro
117 #define LCR_ACCESS_EFR 0xBF // Load this value to access DLL,DLM,
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| H A D | io_edgeport.c | 2220 MAKE_CMD_WRITE_REG(&currCmd, &cmdLen, number, DLL, LOW8(divisor));
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| /linux-master/arch/x86/kernel/ |
| H A D | early_printk.c | 94 #define DLL 0 /* Divisor Latch Low */ macro
141 serial_out(early_serial_base, DLL, divisor & 0xff);
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| /linux-master/drivers/net/hamradio/ |
| H A D | baycom_ser_fdx.c | 102 #define DLL(iobase) (iobase+0) macro
174 outb(divisor, DLL(dev->base_addr));
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| H A D | baycom_ser_hdx.c | 88 #define DLL(iobase) (iobase+0) macro
159 outb(divisor, DLL(dev->base_addr));
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| H A D | yam.c | 159 #define DLL(iobase) (iobase+0) macro
295 outb(1, DLL(iobase));
467 outb(divisor, DLL(dev->base_addr));
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