| /linux-master/drivers/gpu/drm/amd/amdgpu/ |
| H A D | dimgrey_cavefish_reg_init.c | 44 adev->reg_offset[DCE_HWIP][i] = (uint32_t *)(&(DCN_BASE.instance[i]));
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| /linux-master/drivers/gpu/drm/amd/include/ |
| H A D | navi10_ip_offset.h | 55 static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | yellow_carp_offset.h | 47 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | renoir_ip_offset.h | 170 static const struct IP_BASE DCN_BASE ={ { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vega10_ip_offset.h | 51 static const struct IP_BASE __maybe_unused DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0, 0 } }, variable in typeref:struct:__maybe_unused
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| H A D | sienna_cichlid_ip_offset.h | 65 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00 } }, variable in typeref:struct:IP_BASE
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| H A D | beige_goby_ip_offset.h | 73 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | dimgrey_cavefish_ip_offset.h | 65 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, variable in typeref:struct:IP_BASE
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| H A D | vangogh_ip_offset.h | 72 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, variable in typeref:struct:IP_BASE
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn21/ |
| H A D | dcn21_resource.c | 1369 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn301/ |
| H A D | dcn301_resource.c | 921 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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| /linux-master/drivers/gpu/drm/amd/display/dc/resource/dcn30/ |
| H A D | dcn30_resource.c | 2253 (DCN_BASE.instance[0].segment[mm ## reg_name ## _BASE_IDX] + mm ## reg_name)
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