/freebsd-11-stable/contrib/gcc/ |
H A D | fp-test.c | 83 volatile long double D1 = 1.0, D2 = 1.0, D3 = 1.0; variable 183 D1 = D2 + D3; 184 D1 = D2 - D3; 185 D1 = D2 * D3; 186 D1 = D2 / D3;
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/ARM/ |
H A D | ARMBaseRegisterInfo.h | 78 case D3: case D2: case D1: case D0:
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H A D | ARMExpandPseudoInsts.cpp | 437 unsigned &D1, unsigned &D2, unsigned &D3) { 442 D3 = TRI->getSubReg(Reg, ARM::dsub_3); 447 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 452 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 457 D3 = TRI->getSubReg(Reg, ARM::dsub_6); 463 D3 = TRI->getSubReg(Reg, ARM::dsub_7); 500 unsigned D0, D1, D2, D3; local 501 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); 508 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead)); 628 unsigned D0, D1, D2, D3; local 435 GetDSubRegs(unsigned Reg, NEONRegSpacing RegSpc, const TargetRegisterInfo *TRI, unsigned &D0, unsigned &D1, unsigned &D2, unsigned &D3) argument 764 unsigned D0, D1, D2, D3; local [all...] |
H A D | ARMCallingConv.cpp | 162 static const MCPhysReg DRegList[] = { ARM::D0, ARM::D1, ARM::D2, ARM::D3,
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/freebsd-11-stable/lib/msun/ld128/ |
H A D | s_expl.c | 173 D3 = 1.66666666666666666666666666666682245e-1L, variable 251 q = x * x2 * D3 + x2 * x2 * (D4 + x * (D5 + x * (D6 +
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/freebsd-11-stable/contrib/llvm-project/llvm/utils/TableGen/ |
H A D | X86RecognizableInstr.h | 46 MAP(D3, 83) \
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64CallingConvention.cpp | 33 AArch64::D3, AArch64::D4, AArch64::D5,
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H A D | AArch64PBQPRegAlloc.cpp | 64 case AArch64::D3:
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H A D | AArch64FastISel.cpp | 3015 { AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Utils/ |
H A D | AArch64BaseInfo.h | 114 case AArch64::D3: return AArch64::B3; 154 case AArch64::B3: return AArch64::D3;
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/freebsd-11-stable/crypto/openssl/crypto/ec/asm/ |
H A D | ecp_nistz256-avx2.pl | 196 vpunpckhqdq $X3, $X2, $T3 # T3 = [D3 C3 D1 C1] 206 vperm2i128 \$0x31, $T3, $T2, $X3 # X3 = [D3 C3 B3 A3] 307 my ($D0,$D1,$D2,$D3, $D4,$D5,$D6,$D7, $D8)=map("%ymm$_",(0..8)); 339 vmovdqa 32*3(%rsi), $D3 352 vpsllq \$23, $D3, $D3 354 vpaddq $D2, $D3, $D3 355 vpaddq $D3, $T1, $D1 # out[1] = (in[2] >> (64*1-shift*2)) ^ (in[3] << shift*3%64) ^ (in[4] << shift*4%64); 367 vpaddq $D7, $T3, $D3 # ou [all...] |
/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 63 D0, D1, D2, D3, D4, D5, D6, D7, 0
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H A D | HexagonGenInsert.cpp | 795 unsigned D3 = std::distance(FromI, FB->end()); 796 return D1+D2+D3;
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H A D | HexagonISelLowering.cpp | 278 .Case("r7:6", Hexagon::D3)
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/MCTargetDesc/ |
H A D | HexagonMCInstrInfo.cpp | 245 case D3: 560 return ((Reg >= Hexagon::D0 && Reg <= Hexagon::D3) ||
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H A D | HexagonMCDuplexInfo.cpp | 681 case Hexagon::D3:
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Hexagon/Disassembler/ |
H A D | HexagonDisassembler.cpp | 585 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3, 596 Hexagon::D0, Hexagon::D1, Hexagon::D2, Hexagon::D3,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/ |
H A D | AArch64MCTargetDesc.cpp | 166 {codeview::RegisterId::ARM64_D3, AArch64::D3},
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/freebsd-11-stable/crypto/openssl/crypto/bn/asm/ |
H A D | pa-risc2.s | 856 B $D3 ;offset 0xa3c 901 $D3
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H A D | pa-risc2W.s | 762 CMPB,*= %r0,%arg2,$D3 ; if (d == 0) 868 $D3
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/freebsd-11-stable/sys/dev/fe/ |
H A D | if_fe.c | 565 #define LNX_CYCLE(D1,D2,D3,D4,K1,K2,K3,K4) \ 566 (LNX_PH(D1,K1,0)|LNX_PH(D2,K2,8)|LNX_PH(D3,K3,16)|LNX_PH(D4,K4,24))
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/Disassembler/ |
H A D | SparcDisassembler.cpp | 82 SP::D2, SP::D18, SP::D3, SP::D19,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/Sparc/AsmParser/ |
H A D | SparcAsmParser.cpp | 149 Sparc::D0, Sparc::D1, Sparc::D2, Sparc::D3,
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/freebsd-11-stable/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/ |
H A D | AArch64Disassembler.cpp | 334 AArch64::D0, AArch64::D1, AArch64::D2, AArch64::D3, AArch64::D4,
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/freebsd-11-stable/contrib/amd/doc/ |
H A D | texinfo.tex | 9295 \DeclareUnicodeCharacter{00D3}{\'O} 9463 \DeclareUnicodeCharacter{01D3}{\v{U}}
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