Searched refs:CRn (Results 1 - 6 of 6) sorted by relevance

/linux-master/arch/arm64/kvm/
H A Dsys_regs.h18 (u32)(x)->CRn, (u32)(x)->CRm, (u32)(x)->Op2)
23 u8 CRn; member in struct:sys_reg_params
33 .CRn = sys_reg_CRn(reg), \
40 .CRn = ((esr) >> 10) & 0xf, \
47 .CRn = ((esr) >> 10) & 0xf, \
65 u8 CRn; member in struct:sys_reg_desc
110 kvm_pr_unimpl("%pV { Op0(%2u), Op1(%2u), CRn(%2u), CRm(%2u), Op2(%2u), func_%s },\n",
112 p->Op0, p->Op1, p->CRn, p->CRm, p->Op2, p->is_write ? "write" : "read");
201 if (i1->CRn != i2->CRn)
241 #define CRn macro
[all...]
H A Dsys_regs.c1020 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
1037 if (r->CRn == 9 && r->CRm == 13) {
1052 } else if (r->CRn == 0 && r->CRm == 9) {
1058 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
1092 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
1096 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
1572 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
2116 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
2120 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2190 * Important: Must be sorted ascending by Op0, Op1, CRn, CR
[all...]
H A Dtrace_handle_exit.h170 __field(u8, CRn)
182 __entry->CRn = reg->CRn;
189 __entry->Op0, __entry->Op1, __entry->CRn,
H A Demulate-nested.c1878 encoding = sys_reg(sr->Op0, sr->Op1, sr->CRn, sr->CRm, sr->Op2);
2102 if (!(params.Op0 == 3 && (params.CRn & 0b1011) == 0b1011))
/linux-master/arch/arm/include/asm/vdso/
H A Dcp15.h14 #define __ACCESS_CP15(CRn, Op1, CRm, Op2) \
15 "mrc", "mcr", __stringify(p15, Op1, %0, CRn, CRm, Op2), u32
/linux-master/arch/arm64/kvm/hyp/nvhe/
H A Dsys_regs.c323 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
327 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
339 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2

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