Searched refs:CPU (Results 1 - 25 of 68) sorted by relevance

123

/linux-master/arch/sparc/kernel/
H A Dcpu.c54 #define CPU(ver, _name) \ macro
68 CPU(0, "Fujitsu MB86900/1A or LSI L64831 SparcKIT-40"),
70 CPU(4, "Fujitsu MB86904"),
71 CPU(5, "Fujitsu TurboSparc MB86907"),
72 CPU(-1, NULL)
88 CPU(0, "LSI Logic Corporation - L64811"),
90 CPU(1, "Cypress/ROSS CY7C601"),
92 CPU(3, "Cypress/ROSS CY7C611"),
94 CPU(0xf, "ROSS HyperSparc RT620"),
95 CPU(
[all...]
/linux-master/tools/testing/selftests/rcutorture/configs/scf/
H A Dver_functions.sh16 echo CPU-hotplug kernel, adding scftorture onoff. 1>&2
/linux-master/tools/testing/selftests/rcutorture/configs/lock/
H A Dver_functions.sh16 echo CPU-hotplug kernel, adding locktorture onoff. 1>&2
/linux-master/arch/arm/mach-versatile/
H A Ddcscb_setup.S28 2: @ Implementation-specific local CPU setup operations should go here,
/linux-master/tools/testing/selftests/rcutorture/configs/rcu/
H A Dver_functions.sh28 echo CPU-hotplug kernel, adding rcutorture onoff. 1>&2
/linux-master/drivers/media/pci/cx18/
H A Dcx18-mailbox.c20 static const char *rpu_str[] = { "APU", "CPU", "EPU", "HPU" };
36 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYPE, 0),
37 API_ENTRY(CPU, CX18_EPU_DEBUG, 0),
38 API_ENTRY(CPU, CX18_CREATE_TASK, 0),
39 API_ENTRY(CPU, CX18_DESTROY_TASK, 0),
40 API_ENTRY(CPU, CX18_CPU_CAPTURE_START, API_SLOW),
41 API_ENTRY(CPU, CX18_CPU_CAPTURE_STOP, API_SLOW),
42 API_ENTRY(CPU, CX18_CPU_CAPTURE_PAUSE, 0),
43 API_ENTRY(CPU, CX18_CPU_CAPTURE_RESUME, 0),
44 API_ENTRY(CPU, CX18_CPU_SET_CHANNEL_TYP
[all...]
H A Dcx18-mailbox.h21 #define CPU 1 macro
28 * This structure is used by CPU to provide completed MDL & buffers information.
H A Dcx18-irq.c26 cx18_api_epu_cmd_irq(cx, CPU);
/linux-master/arch/arm/kernel/
H A Dhyp-stub.S16 * For the kernel proper, we need to find out the CPU boot mode long after
29 * Save the primary CPU boot mode. Requires 2 scratch registers.
38 * Compare the current mode with the one saved on the primary CPU.
46 cmp \mode, \reg1 @ matches primary CPU boot mode?
57 * The zImage loader only runs on one CPU, so we don't bother with mult-CPU
73 @ Call this from the primary CPU
93 * Once we have given up on one CPU, we do not try to install the
102 retne lr @ give up if the CPU is not in HYP mode
108 * Eventually, CPU
[all...]
/linux-master/tools/testing/selftests/rcutorture/bin/
H A Dkvm-test-1-run-batch.sh63 print "echo No CPU-affinity information, so no taskset command.";
69 print "echo " scenario ": Bogus CPU-affinity information, so no taskset command.";
/linux-master/arch/arm/common/
H A Dmcpm_head.S27 1902: .asciz "CPU"
58 mla r4, r3, r10, r9 @ r4 = canonical CPU index
62 /* We didn't expect this CPU. Try to cheaply make it quiet. */
90 @ Signal that this CPU is coming UP:
97 @ state, because there is at least one active CPU (this CPU).
125 @ Any CPU trying to take the cluster into CLUSTER_GOING_DOWN from this
178 @ If a platform-specific CPU setup hook is needed, it is
182 mov r0, #0 @ first (CPU) affinity level
186 @ Mark the CPU a
[all...]
H A Dvlock.S51 @ r1: CPU ID (0-based index within cluster)
/linux-master/tools/rcu/
H A Dextract-stall.sh5 echo Extract any RCU CPU stall warnings present in specified file.
/linux-master/tools/testing/selftests/sgx/
H A Dtest_encl_bootstrap.S13 .fill 1, 8, 0 # STATE (set by CPU)
16 .fill 1, 4, 0 # CSSA (set by CPU)
27 .fill 1, 8, 0 # STATE (set by CPU)
30 .fill 1, 4, 0 # CSSA (set by CPU)
/linux-master/arch/arm/mach-mvebu/
H A Dpmsu_ll.S15 orr r1, r1, #0x8 @ SCU CPU Power Status Register
16 mrc p15, 0, r0, cr0, cr0, 5 @ get the CPU ID
/linux-master/arch/arm/mach-shmobile/
H A Dheadsmp-scu.S15 * First we turn on L1 cache coherency for our CPU. Then we jump to
27 bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
/linux-master/tools/testing/selftests/cgroup/
H A Dtest_cpuset_prs.sh28 NR_CPUS=$(lscpu | grep "^CPU(s):" | sed -e "s/.*:[[:space:]]*//")
67 # create partition under root cgroup because of the CPU exclusivity rule.
162 # O<c>=<v> = Write <v> to CPU online file of <c>
188 # CPU offlining cases:
278 # Local partition CPU change tests
366 CPU=${1%=*}
368 CPUFILE=//sys/devices/system/cpu/cpu${CPU}/online
371 OFFLINE_CPUS="$OFFLINE_CPUS $CPU"
374 OFFLINE_CPUS=$(echo $CPU $CPU
[all...]
/linux-master/tools/perf/tests/
H A Dhists_output.c134 #define CPU(he) (he->cpu) macro
256 * Overhead CPU Command: Pid
282 CPU(he) == 1 && PID(he) == 100 && he->stat.period == 300);
287 CPU(he) == 0 && PID(he) == 100 && he->stat.period == 100);
488 * CPU Command: Pid Command Shared Object Symbol
518 CPU(he) == 0 && PID(he) == 100 &&
525 CPU(he) == 2 && PID(he) == 200 &&
532 CPU(he) == 1 && PID(he) == 300 &&
539 CPU(he) == 0 && PID(he) == 300 &&
546 CPU(h
[all...]
/linux-master/arch/arm/mach-sa1100/
H A Dsleep.S50 @ Adjust memory timing before lowering CPU clock
53 @ delay 90us and set CPU PLL to lowest speed
137 @ about 7 ns out of the entire time that the CPU is running!
/linux-master/drivers/clk/mxs/
H A Dclk-imx23.c23 #define CPU (CLKCTRL + 0x0020) macro
49 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
125 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
126 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
H A Dclk-imx28.c23 #define CPU (CLKCTRL + 0x0050) macro
84 writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
190 clks[cpu_pll] = mxs_clk_div("cpu_pll", "ref_cpu", CPU, 0, 6, 28);
191 clks[cpu_xtal] = mxs_clk_div("cpu_xtal", "ref_xtal", CPU, 16, 10, 29);
/linux-master/tools/perf/tests/shell/
H A Dstat+shadow_stat.sh57 grep ^CPU | \
/linux-master/arch/arm/mach-tegra/
H A Dreset-handler.S28 * CPU boot vector when restarting the a CPU following
33 * r8: CPU part number
48 /* Clear the flow controller flags for this CPU. */
56 @ & ext flags for CPU power mgnt
121 * Common handler for all CPU reset events.
127 * R7 = CPU present (to the OS) mask
128 * R8 = CPU in LP1 state mask
129 * R9 = CPU in LP2 state mask
130 * R10 = CPU numbe
[all...]
/linux-master/Documentation/trace/
H A Dfunction-graph-fold.vim12 " single-CPU trace (e.g. trace-cmd report --cpu 1).
/linux-master/arch/mips/include/asm/fw/arc/
H A Dhinv.h31 CPU, enumerator in enum:configtype

Completed in 941 milliseconds

123