Searched refs:CLK_OPS_PARENT_ENABLE (Results 1 - 25 of 35) sorted by relevance

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/linux-master/drivers/clk/stm32/
H A Dclk-stm32mp13.c948 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
956 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
964 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
972 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
980 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
988 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
996 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1004 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1012 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPARENT),
1020 CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_NO_REPAREN
[all...]
H A Dclk-stm32mp1.c1390 COMPOSITE(_id, _name, _parents, CLK_OPS_PARENT_ENABLE |\
1834 MUX(CK_PER, "ck_per", per_src, CLK_OPS_PARENT_ENABLE,
1837 MUX(CK_MPU, "ck_mpu", cpu_src, CLK_OPS_PARENT_ENABLE |
1841 CLK_OPS_PARENT_ENABLE,
1847 CLK_OPS_PARENT_ENABLE,
2051 COMPOSITE(NO_ID, "ck_ker_eth", eth_src, CLK_OPS_PARENT_ENABLE |
2059 DIV(ETHPTP_K, "ethptp_k", "ck_ker_eth", CLK_OPS_PARENT_ENABLE |
2063 COMPOSITE(RTC, "ck_rtc", rtc_src, CLK_OPS_PARENT_ENABLE,
2069 COMPOSITE(CK_MCO1, "ck_mco1", mco1_src, CLK_OPS_PARENT_ENABLE |
2075 COMPOSITE(CK_MCO2, "ck_mco2", mco2_src, CLK_OPS_PARENT_ENABLE |
[all...]
/linux-master/drivers/clk/qcom/
H A Dlpass-gfm-sm8250.c75 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
95 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
115 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
135 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
155 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
175 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Ddispcc-sm6115.c162 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
255 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE | CLK_GET_RATE_NOCACHE,
H A Ddispcc-sm6375.c153 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
210 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Ddispcc-qcm2290.c136 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
229 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Dgpucc-msm8998.c147 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Dgpucc-sdm660.c116 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Ddispcc-sm6350.c309 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
388 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE | CLK_OPS_PARENT_ENABLE,
H A Dgpucc-sm6375.c181 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Dgpucc-sm6125.c166 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Dgcc-sm6115.c726 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
749 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
764 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
779 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
801 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
816 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
831 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
846 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1035 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
1057 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
[all...]
H A Dgcc-qcm2290.c766 .flags = CLK_OPS_PARENT_ENABLE,
781 .flags = CLK_OPS_PARENT_ENABLE,
796 .flags = CLK_OPS_PARENT_ENABLE,
811 .flags = CLK_OPS_PARENT_ENABLE,
965 .flags = CLK_OPS_PARENT_ENABLE,
1247 .flags = CLK_OPS_PARENT_ENABLE,
H A Dgpucc-sm6115.c232 .flags = CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE,
H A Dlpassaudiocc-sc7280.c252 .flags = CLK_OPS_PARENT_ENABLE,
/linux-master/drivers/clk/mediatek/
H A Dclk-mt8195-imp_iic_wrap.c21 &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
H A Dclk-mt8188-imp_iic_wrap.c24 &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
H A Dclk-mt8192-imp_iic_wrap.c23 &mtk_clk_gate_ops_setclr, CLK_OPS_PARENT_ENABLE)
/linux-master/drivers/clk/imx/
H A Dclk.h185 __imx_clk_hw_gate2(name, parent, reg, shift, 0x3, CLK_OPS_PARENT_ENABLE, shared_count)
191 __imx_clk_hw_gate(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE, 0)
197 imx_clk_hw_gate2_flags(name, parent, reg, shift, flags | CLK_OPS_PARENT_ENABLE)
212 __imx_clk_hw_mux(name, reg, shift, width, parents, num_parents, flags | CLK_OPS_PARENT_ENABLE, 0)
219 CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE)
410 (CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
471 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
H A Dclk-gate-93.c180 init.flags = flags | CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE;
H A Dclk-imx7d.c709 hws[IMX7D_IPG_ROOT_CLK] = imx_clk_hw_divider_flags("ipg_root_clk", "ahb_root_clk", base + 0x9080, 0, 2, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE | CLK_SET_RATE_PARENT);
773 hws[IMX7D_ARM_A7_ROOT_CLK] = imx_clk_hw_gate2_flags("arm_a7_root_clk", "arm_a7_div", base + 0x4000, 0, CLK_OPS_PARENT_ENABLE);
775 hws[IMX7D_MAIN_AXI_ROOT_CLK] = imx_clk_hw_gate2_flags("main_axi_root_clk", "axi_post_div", base + 0x4040, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
780 hws[IMX7D_DRAM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_root_clk", "dram_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
781 hws[IMX7D_DRAM_PHYM_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_root_clk", "dram_phym_cg", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
782 hws[IMX7D_DRAM_PHYM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_phym_alt_root_clk", "dram_phym_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
783 hws[IMX7D_DRAM_ALT_ROOT_CLK] = imx_clk_hw_gate2_flags("dram_alt_root_clk", "dram_alt_post_div", base + 0x4130, 0, CLK_IS_CRITICAL | CLK_OPS_PARENT_ENABLE);
H A Dclk-imx8mq.c576 hws[IMX8MQ_CLK_VPU_G1_ROOT] = imx_clk_hw_gate2_flags("vpu_g1_root_clk", "vpu_g1", base + 0x4560, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
578 hws[IMX8MQ_CLK_VPU_G2_ROOT] = imx_clk_hw_gate2_flags("vpu_g2_root_clk", "vpu_g2", base + 0x45a0, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
584 hws[IMX8MQ_CLK_VPU_DEC_ROOT] = imx_clk_hw_gate2_flags("vpu_dec_root_clk", "vpu_bus", base + 0x4630, 0, CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
H A Dclk-imx7ulp.c108 hws[IMX7ULP_CLK_DDR_SEL] = imx_clk_hw_mux_flags("ddr_sel", base + 0x30, 24, 2, ddr_sels, ARRAY_SIZE(ddr_sels), CLK_SET_RATE_PARENT | CLK_OPS_PARENT_ENABLE);
/linux-master/drivers/clk/
H A Dclk.c340 if ((core->flags & CLK_OPS_PARENT_ENABLE) && core->parent)
1492 if (core->flags & CLK_OPS_PARENT_ENABLE)
1519 if (core->flags & CLK_OPS_PARENT_ENABLE)
2123 * 1. enable parents for CLK_OPS_PARENT_ENABLE clock
2142 /* enable old_parent & parent if CLK_OPS_PARENT_ENABLE is set */
2143 if (core->flags & CLK_OPS_PARENT_ENABLE) {
2175 /* re-balance ref counting if CLK_OPS_PARENT_ENABLE is set */
2176 if (core->flags & CLK_OPS_PARENT_ENABLE) {
2452 if (core->flags & CLK_OPS_PARENT_ENABLE)
2469 if (core->flags & CLK_OPS_PARENT_ENABLE)
[all...]
/linux-master/drivers/clk/xilinx/
H A Dxlnx_vcu.c540 CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE);

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