/linux-master/drivers/clk/hisilicon/ |
H A D | clk-hi3620.c | 95 { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, }, 96 { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, }, 97 { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, }, 98 { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, }, 99 { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, }, 100 { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, }, 101 { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, }, 102 { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, }, 103 { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, }, 104 { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, }, [all...] |
H A D | clk-hi3660.c | 271 CLK_MUX_HIWORD_MASK, }, 274 CLK_MUX_HIWORD_MASK, }, 277 CLK_MUX_HIWORD_MASK, }, 280 CLK_MUX_HIWORD_MASK, }, 283 CLK_MUX_HIWORD_MASK, }, 286 CLK_MUX_HIWORD_MASK, }, 289 CLK_MUX_HIWORD_MASK, }, 292 CLK_MUX_HIWORD_MASK, }, 295 CLK_MUX_HIWORD_MASK, }, 298 CLK_MUX_HIWORD_MASK, }, [all...] |
H A D | clk-hi3670.c | 420 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, }, 423 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, }, 426 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, }, 429 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, }, 432 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, }, 435 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, }, 438 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, }, 441 0x100, 0, 1, CLK_MUX_HIWORD_MASK, }, 444 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, }, 447 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, }, [all...] |
H A D | clk-hi6220.c | 153 { HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,}, 154 { HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,}, 155 { HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,}, 156 { HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,}, 157 { HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,}, 158 { HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,}, 159 { HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,}, 160 { HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,}, 161 { HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,}, 162 { HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,}, [all...] |
/linux-master/drivers/clk/rockchip/ |
H A D | clk-muxgrf.c | 44 if (mux->flags & CLK_MUX_HIWORD_MASK)
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H A D | clk-rk3036.c | 145 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3228.c | 179 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3128.c | 169 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3188.c | 237 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-px30.c | 204 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3288.c | 245 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3368.c | 151 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3328.c | 232 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rv1108.c | 162 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3308.c | 194 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rv1126.c | 211 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-pll.c | 1102 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
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H A D | clk-rk3399.c | 240 #define MFLAGS CLK_MUX_HIWORD_MASK
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H A D | clk-rk3568.c | 346 #define MFLAGS CLK_MUX_HIWORD_MASK
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/linux-master/drivers/clk/zynqmp/ |
H A D | clk-mux-zynqmp.c | 109 ccf_flag |= CLK_MUX_HIWORD_MASK;
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/linux-master/drivers/clk/ |
H A D | clk-mux.c | 111 if (mux->flags & CLK_MUX_HIWORD_MASK) { 162 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
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/linux-master/drivers/clk/ti/ |
H A D | mux.c | 73 if (mux->flags & CLK_MUX_HIWORD_MASK) {
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/linux-master/drivers/clk/renesas/ |
H A D | rzg2l-cpg.h | 160 .mux_flags = CLK_MUX_HIWORD_MASK)
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H A D | r9a08g045-cpg.c | 59 .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
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/linux-master/include/linux/ |
H A D | clk-provider.h | 955 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this 981 #define CLK_MUX_HIWORD_MASK BIT(2) macro
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