Searched refs:CLK_MUX_HIWORD_MASK (Results 1 - 25 of 26) sorted by relevance

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/linux-master/drivers/clk/hisilicon/
H A Dclk-hi3620.c95 { HI3620_UART0_MUX, "uart0_mux", uart0_mux_p, ARRAY_SIZE(uart0_mux_p), CLK_SET_RATE_PARENT, 0x100, 7, 1, CLK_MUX_HIWORD_MASK, },
96 { HI3620_UART1_MUX, "uart1_mux", uart1_mux_p, ARRAY_SIZE(uart1_mux_p), CLK_SET_RATE_PARENT, 0x100, 8, 1, CLK_MUX_HIWORD_MASK, },
97 { HI3620_UART2_MUX, "uart2_mux", uart2_mux_p, ARRAY_SIZE(uart2_mux_p), CLK_SET_RATE_PARENT, 0x100, 9, 1, CLK_MUX_HIWORD_MASK, },
98 { HI3620_UART3_MUX, "uart3_mux", uart3_mux_p, ARRAY_SIZE(uart3_mux_p), CLK_SET_RATE_PARENT, 0x100, 10, 1, CLK_MUX_HIWORD_MASK, },
99 { HI3620_UART4_MUX, "uart4_mux", uart4_mux_p, ARRAY_SIZE(uart4_mux_p), CLK_SET_RATE_PARENT, 0x100, 11, 1, CLK_MUX_HIWORD_MASK, },
100 { HI3620_SPI0_MUX, "spi0_mux", spi0_mux_p, ARRAY_SIZE(spi0_mux_p), CLK_SET_RATE_PARENT, 0x100, 12, 1, CLK_MUX_HIWORD_MASK, },
101 { HI3620_SPI1_MUX, "spi1_mux", spi1_mux_p, ARRAY_SIZE(spi1_mux_p), CLK_SET_RATE_PARENT, 0x100, 13, 1, CLK_MUX_HIWORD_MASK, },
102 { HI3620_SPI2_MUX, "spi2_mux", spi2_mux_p, ARRAY_SIZE(spi2_mux_p), CLK_SET_RATE_PARENT, 0x100, 14, 1, CLK_MUX_HIWORD_MASK, },
103 { HI3620_SAXI_MUX, "saxi_mux", saxi_mux_p, ARRAY_SIZE(saxi_mux_p), CLK_SET_RATE_PARENT, 0x100, 15, 1, CLK_MUX_HIWORD_MASK, },
104 { HI3620_PWM0_MUX, "pwm0_mux", pwm0_mux_p, ARRAY_SIZE(pwm0_mux_p), CLK_SET_RATE_PARENT, 0x104, 10, 1, CLK_MUX_HIWORD_MASK, },
[all...]
H A Dclk-hi3660.c271 CLK_MUX_HIWORD_MASK, },
274 CLK_MUX_HIWORD_MASK, },
277 CLK_MUX_HIWORD_MASK, },
280 CLK_MUX_HIWORD_MASK, },
283 CLK_MUX_HIWORD_MASK, },
286 CLK_MUX_HIWORD_MASK, },
289 CLK_MUX_HIWORD_MASK, },
292 CLK_MUX_HIWORD_MASK, },
295 CLK_MUX_HIWORD_MASK, },
298 CLK_MUX_HIWORD_MASK, },
[all...]
H A Dclk-hi3670.c420 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
423 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },
426 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },
429 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },
432 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },
435 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },
438 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },
441 0x100, 0, 1, CLK_MUX_HIWORD_MASK, },
444 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
447 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
[all...]
H A Dclk-hi6220.c153 { HI6220_HIFI_SRC, "hifi_src", hifi_src, ARRAY_SIZE(hifi_src), CLK_SET_RATE_PARENT, 0x400, 0, 1, CLK_MUX_HIWORD_MASK,},
154 { HI6220_UART1_SRC, "uart1_src", uart1_src, ARRAY_SIZE(uart1_src), CLK_SET_RATE_PARENT, 0x400, 1, 1, CLK_MUX_HIWORD_MASK,},
155 { HI6220_UART2_SRC, "uart2_src", uart2_src, ARRAY_SIZE(uart2_src), CLK_SET_RATE_PARENT, 0x400, 2, 1, CLK_MUX_HIWORD_MASK,},
156 { HI6220_UART3_SRC, "uart3_src", uart3_src, ARRAY_SIZE(uart3_src), CLK_SET_RATE_PARENT, 0x400, 3, 1, CLK_MUX_HIWORD_MASK,},
157 { HI6220_UART4_SRC, "uart4_src", uart4_src, ARRAY_SIZE(uart4_src), CLK_SET_RATE_PARENT, 0x400, 4, 1, CLK_MUX_HIWORD_MASK,},
158 { HI6220_MMC0_MUX0, "mmc0_mux0", mmc0_mux0_p, ARRAY_SIZE(mmc0_mux0_p), CLK_SET_RATE_PARENT, 0x400, 5, 1, CLK_MUX_HIWORD_MASK,},
159 { HI6220_MMC1_MUX0, "mmc1_mux0", mmc1_mux0_p, ARRAY_SIZE(mmc1_mux0_p), CLK_SET_RATE_PARENT, 0x400, 11, 1, CLK_MUX_HIWORD_MASK,},
160 { HI6220_MMC2_MUX0, "mmc2_mux0", mmc2_mux0_p, ARRAY_SIZE(mmc2_mux0_p), CLK_SET_RATE_PARENT, 0x400, 12, 1, CLK_MUX_HIWORD_MASK,},
161 { HI6220_MMC0_MUX1, "mmc0_mux1", mmc0_mux1_p, ARRAY_SIZE(mmc0_mux1_p), CLK_SET_RATE_PARENT, 0x400, 13, 1, CLK_MUX_HIWORD_MASK,},
162 { HI6220_MMC1_MUX1, "mmc1_mux1", mmc1_mux1_p, ARRAY_SIZE(mmc1_mux1_p), CLK_SET_RATE_PARENT, 0x400, 14, 1, CLK_MUX_HIWORD_MASK,},
[all...]
/linux-master/drivers/clk/rockchip/
H A Dclk-muxgrf.c44 if (mux->flags & CLK_MUX_HIWORD_MASK)
H A Dclk-rk3036.c145 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3228.c179 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3128.c169 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3188.c237 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-px30.c204 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3288.c245 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3368.c151 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3328.c232 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rv1108.c162 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3308.c194 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rv1126.c211 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-pll.c1102 pll_mux->flags |= CLK_MUX_HIWORD_MASK;
H A Dclk-rk3399.c240 #define MFLAGS CLK_MUX_HIWORD_MASK
H A Dclk-rk3568.c346 #define MFLAGS CLK_MUX_HIWORD_MASK
/linux-master/drivers/clk/zynqmp/
H A Dclk-mux-zynqmp.c109 ccf_flag |= CLK_MUX_HIWORD_MASK;
/linux-master/drivers/clk/
H A Dclk-mux.c111 if (mux->flags & CLK_MUX_HIWORD_MASK) {
162 if (clk_mux_flags & CLK_MUX_HIWORD_MASK) {
/linux-master/drivers/clk/ti/
H A Dmux.c73 if (mux->flags & CLK_MUX_HIWORD_MASK) {
/linux-master/drivers/clk/renesas/
H A Drzg2l-cpg.h160 .mux_flags = CLK_MUX_HIWORD_MASK)
H A Dr9a08g045-cpg.c59 .mux_flags = CLK_MUX_HIWORD_MASK | (_mux_flags), \
/linux-master/include/linux/
H A Dclk-provider.h955 * CLK_MUX_HIWORD_MASK - The mux settings are only in lower 16-bit of this
981 #define CLK_MUX_HIWORD_MASK BIT(2) macro

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