Searched refs:BIT_28 (Results 1 - 4 of 4) sorted by path

/freebsd-11-stable/sys/dev/msk/
H A Dif_mskreg.h162 #define BIT_28 (1 << 28) macro
264 #define PCI_Y2_PHY1_COMA BIT_28 /* Set PHY 1 to Coma Mode (YUKON-2) */
346 #define PCI_CTL_TIM_VMAIN_AV1 BIT_28 /* Bit 28..27: Timer Vmain_av Mask */
348 #define PCI_CTL_TIM_VMAIN_AV_MSK (BIT_28 | BIT_27)
862 #define Y2_IS_SENSOR BIT_28 /* Sensor interrupt */
1130 #define F_ALM_FULL BIT_28 /* Rx FIFO: almost full */
2080 #define GPC_SEL_BDT BIT_28 /* Select Bi-Dir. Transfer for MDC/MDIO */
2297 #define BMU_IRQ_EOB BIT_28 /* Req "End of Buffer" IRQ */
/freebsd-11-stable/sys/dev/qlxgb/
H A Dqla_def.h66 #define BIT_28 (0x1 << 28) macro
/freebsd-11-stable/sys/dev/qlxgbe/
H A Dql_def.h66 #define BIT_28 (0x1 << 28) macro
/freebsd-11-stable/sys/dev/qlxge/
H A Dqls_hw.h82 #define BIT_28 (0x1 << 28) macro
501 #define Q81_CTL_RD_RSS_TCP_IPV4 BIT_28

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