Searched refs:BIT_15 (Results 1 - 5 of 5) sorted by relevance

/freebsd-11-stable/sys/dev/qlxge/
H A Dqls_hw.h54 #define BIT_15 (0x1 << 15) macro
69 #define BIT_15 (0x1 << 15) macro
198 #define Q81_CTL_RESET_FUNC BIT_15
206 #define Q81_CTL_FUNC_SPECIFIC_FE BIT_15
288 #define Q81_CTL_INTRE_EN BIT_15
377 #define Q81_CTL_STOP_CQ_EN BIT_15
491 #define Q81_CTL_RD_BCAST_OR_MCAST_MATCH BIT_15
530 #define Q81_WQ_ICB_RSS_V BIT_15
594 #define Q81_RSS_ICB_FLAGS_RT6 BIT_15
618 #define Q81_TXB_DESC_FLAGS_E BIT_15
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/freebsd-11-stable/sys/dev/msk/
H A Dif_mskreg.h175 #define BIT_15 (1 << 15) macro
278 #define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
331 #define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
787 #define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
999 #define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
1098 #define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
1221 #define WOL_CTL_LINK_CHG_OCC BIT_15
1343 #define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
1399 #define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */
1409 #define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enabl
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/freebsd-11-stable/sys/dev/qlxgb/
H A Dqla_def.h53 #define BIT_15 (0x1 << 15) macro
/freebsd-11-stable/sys/dev/qlxgbe/
H A Dql_def.h53 #define BIT_15 (0x1 << 15) macro
H A Dql_hw.h961 #define Q8_PORT_CFG_BITS_AUTONEG BIT_15

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