Searched refs:BIT7 (Results 1 - 25 of 33) sorted by relevance

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/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h38 #define BIT7 0x00000080 macro
H A Dhalbtc8821a2ant.h8 #define BT_INFO_8821A_2ANT_B_FTP BIT7
H A Dhalbtc8723b1ant.h7 #define BT_INFO_8723B_1ANT_B_FTP BIT7
H A Dhalbtc8723b2ant.h10 #define BT_INFO_8723B_2ANT_B_FTP BIT7
H A Dhalbtc8821a1ant.h8 #define BT_INFO_8821A_1ANT_B_FTP BIT7
H A Dhalbtc8192e2ant.h7 #define BT_INFO_8192E_2ANT_B_FTP BIT7
/linux-master/drivers/video/fbdev/via/
H A Dvia_utility.c138 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
148 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
193 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7);
203 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7);
H A Dlcd.c376 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6);
388 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7);
609 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7);
618 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7);
625 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7);
637 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7);
661 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7);
670 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7);
680 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7);
692 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7);
[all...]
H A Ddvi.c55 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7);
62 BIT5 + BIT6 + BIT7);
453 viafb_write_reg_mask(CR91, VIACR, 0, BIT7);
H A Dhw.c466 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7);
471 viafb_write_reg_mask(CR11, VIACR, 0, BIT7);
945 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7);
1669 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6);
1676 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6);
2034 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7);
2042 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7);
H A Dshare.h21 #define BIT7 0x80 macro
/linux-master/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h53 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* disable HWPDN 0x04[15]= 0*/ \
94 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
114 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0}, /*clear suspend enable and power down enable*/ \
129 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/* 0x04[15] = 1*/
134 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0},/* 0x04[15] = 0*/
162 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0}, /*Polling 0x109[7]= 0 TSF in 40M*/\
163 {0x0029, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0}, /*. 0x29[7:6] = 2b'00 enable BB clock*/\
192 {0x0109, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7},/*pollin
[all...]
H A Drtl8723b_spec.h207 #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */
H A Dosdep_service.h24 #define BIT7 0x00000080 macro
H A Dhal_com_reg.h527 #define HSISR_PDNINT BIT7
554 #define RRSR_18M BIT7
708 #define IMR_TBDOK BIT7 /* Transmit Beacon OK interrupt */
755 #define RCR_CBSSID_BCN BIT7 /* Accept BSSID match packet (Rx beacon, probe rsp) */
1285 #define SDIO_HIMR_TXBCNERR_MSK BIT7
1307 #define SDIO_HISR_TXBCNERR BIT7
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h32 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
93 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
152 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
213 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
218 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
282 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
285 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
401 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
499 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7,
[all...]
/linux-master/drivers/staging/rtl8723bs/hal/
H A DHalBtc8723b2Ant.h8 #define BT_INFO_8723B_2ANT_B_FTP BIT7
H A DHalBtc8723b1Ant.h8 #define BT_INFO_8723B_1ANT_B_FTP BIT7
H A DHalHWImg8723B_MAC.c18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
H A DHal8723BReg.h396 #define IMR_HIGHDOK_8723B BIT7 /* High Queue DMA OK */
H A DHalHWImg8723B_RF.c18 ((pDM_Odm->BoardType & BIT7) >> 7) << 2 | /* _ALNA */
/linux-master/drivers/scsi/
H A Ddc395x.h69 #define BIT7 0x00000080 macro
137 #define DATAOUT BIT7
/linux-master/include/uapi/linux/
H A Dsynclink.h26 #define BIT7 0x0080 macro
/linux-master/lib/zstd/common/
H A Dzstd_internal.h66 #define BIT7 128 macro
/linux-master/drivers/tty/
H A Dsynclink_gt.c388 #define IRQ_DSR BIT7
2782 val |= BIT7;
2784 val &= ~BIT7;
4028 val |= BIT7;
4179 val |= BIT7;
4296 val |= BIT7; /* 100, txclk = DPLL Input */
4319 val = BIT7; break;
4322 val = BIT7 + BIT6; break;
4446 val |= BIT7 + BIT6 + BIT5; /* 1110 */

Completed in 366 milliseconds

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