1/* SPDX-License-Identifier: GPL-1.0+ WITH Linux-syscall-note */ 2/* 3 * SyncLink Multiprotocol Serial Adapter Driver 4 * 5 * $Id: synclink.h,v 3.14 2006/07/17 20:15:43 paulkf Exp $ 6 * 7 * Copyright (C) 1998-2000 by Microgate Corporation 8 * 9 * Redistribution of this file is permitted under 10 * the terms of the GNU Public License (GPL) 11 */ 12 13#ifndef _UAPI_SYNCLINK_H_ 14#define _UAPI_SYNCLINK_H_ 15#define SYNCLINK_H_VERSION 3.6 16 17#include <linux/types.h> 18 19#define BIT0 0x0001 20#define BIT1 0x0002 21#define BIT2 0x0004 22#define BIT3 0x0008 23#define BIT4 0x0010 24#define BIT5 0x0020 25#define BIT6 0x0040 26#define BIT7 0x0080 27#define BIT8 0x0100 28#define BIT9 0x0200 29#define BIT10 0x0400 30#define BIT11 0x0800 31#define BIT12 0x1000 32#define BIT13 0x2000 33#define BIT14 0x4000 34#define BIT15 0x8000 35#define BIT16 0x00010000 36#define BIT17 0x00020000 37#define BIT18 0x00040000 38#define BIT19 0x00080000 39#define BIT20 0x00100000 40#define BIT21 0x00200000 41#define BIT22 0x00400000 42#define BIT23 0x00800000 43#define BIT24 0x01000000 44#define BIT25 0x02000000 45#define BIT26 0x04000000 46#define BIT27 0x08000000 47#define BIT28 0x10000000 48#define BIT29 0x20000000 49#define BIT30 0x40000000 50#define BIT31 0x80000000 51 52 53#define HDLC_MAX_FRAME_SIZE 65535 54#define MAX_ASYNC_TRANSMIT 4096 55#define MAX_ASYNC_BUFFER_SIZE 4096 56 57#define ASYNC_PARITY_NONE 0 58#define ASYNC_PARITY_EVEN 1 59#define ASYNC_PARITY_ODD 2 60#define ASYNC_PARITY_SPACE 3 61 62#define HDLC_FLAG_UNDERRUN_ABORT7 0x0000 63#define HDLC_FLAG_UNDERRUN_ABORT15 0x0001 64#define HDLC_FLAG_UNDERRUN_FLAG 0x0002 65#define HDLC_FLAG_UNDERRUN_CRC 0x0004 66#define HDLC_FLAG_SHARE_ZERO 0x0010 67#define HDLC_FLAG_AUTO_CTS 0x0020 68#define HDLC_FLAG_AUTO_DCD 0x0040 69#define HDLC_FLAG_AUTO_RTS 0x0080 70#define HDLC_FLAG_RXC_DPLL 0x0100 71#define HDLC_FLAG_RXC_BRG 0x0200 72#define HDLC_FLAG_RXC_TXCPIN 0x8000 73#define HDLC_FLAG_RXC_RXCPIN 0x0000 74#define HDLC_FLAG_TXC_DPLL 0x0400 75#define HDLC_FLAG_TXC_BRG 0x0800 76#define HDLC_FLAG_TXC_TXCPIN 0x0000 77#define HDLC_FLAG_TXC_RXCPIN 0x0008 78#define HDLC_FLAG_DPLL_DIV8 0x1000 79#define HDLC_FLAG_DPLL_DIV16 0x2000 80#define HDLC_FLAG_DPLL_DIV32 0x0000 81#define HDLC_FLAG_HDLC_LOOPMODE 0x4000 82 83#define HDLC_CRC_NONE 0 84#define HDLC_CRC_16_CCITT 1 85#define HDLC_CRC_32_CCITT 2 86#define HDLC_CRC_MASK 0x00ff 87#define HDLC_CRC_RETURN_EX 0x8000 88 89#define RX_OK 0 90#define RX_CRC_ERROR 1 91 92#define HDLC_TXIDLE_FLAGS 0 93#define HDLC_TXIDLE_ALT_ZEROS_ONES 1 94#define HDLC_TXIDLE_ZEROS 2 95#define HDLC_TXIDLE_ONES 3 96#define HDLC_TXIDLE_ALT_MARK_SPACE 4 97#define HDLC_TXIDLE_SPACE 5 98#define HDLC_TXIDLE_MARK 6 99#define HDLC_TXIDLE_CUSTOM_8 0x10000000 100#define HDLC_TXIDLE_CUSTOM_16 0x20000000 101 102#define HDLC_ENCODING_NRZ 0 103#define HDLC_ENCODING_NRZB 1 104#define HDLC_ENCODING_NRZI_MARK 2 105#define HDLC_ENCODING_NRZI_SPACE 3 106#define HDLC_ENCODING_NRZI HDLC_ENCODING_NRZI_SPACE 107#define HDLC_ENCODING_BIPHASE_MARK 4 108#define HDLC_ENCODING_BIPHASE_SPACE 5 109#define HDLC_ENCODING_BIPHASE_LEVEL 6 110#define HDLC_ENCODING_DIFF_BIPHASE_LEVEL 7 111 112#define HDLC_PREAMBLE_LENGTH_8BITS 0 113#define HDLC_PREAMBLE_LENGTH_16BITS 1 114#define HDLC_PREAMBLE_LENGTH_32BITS 2 115#define HDLC_PREAMBLE_LENGTH_64BITS 3 116 117#define HDLC_PREAMBLE_PATTERN_NONE 0 118#define HDLC_PREAMBLE_PATTERN_ZEROS 1 119#define HDLC_PREAMBLE_PATTERN_FLAGS 2 120#define HDLC_PREAMBLE_PATTERN_10 3 121#define HDLC_PREAMBLE_PATTERN_01 4 122#define HDLC_PREAMBLE_PATTERN_ONES 5 123 124#define MGSL_MODE_ASYNC 1 125#define MGSL_MODE_HDLC 2 126#define MGSL_MODE_MONOSYNC 3 127#define MGSL_MODE_BISYNC 4 128#define MGSL_MODE_RAW 6 129#define MGSL_MODE_BASE_CLOCK 7 130#define MGSL_MODE_XSYNC 8 131 132#define MGSL_BUS_TYPE_ISA 1 133#define MGSL_BUS_TYPE_EISA 2 134#define MGSL_BUS_TYPE_PCI 5 135 136#define MGSL_INTERFACE_MASK 0xf 137#define MGSL_INTERFACE_DISABLE 0 138#define MGSL_INTERFACE_RS232 1 139#define MGSL_INTERFACE_V35 2 140#define MGSL_INTERFACE_RS422 3 141#define MGSL_INTERFACE_RTS_EN 0x10 142#define MGSL_INTERFACE_LL 0x20 143#define MGSL_INTERFACE_RL 0x40 144#define MGSL_INTERFACE_MSB_FIRST 0x80 145 146typedef struct _MGSL_PARAMS 147{ 148 /* Common */ 149 150 unsigned long mode; /* Asynchronous or HDLC */ 151 unsigned char loopback; /* internal loopback mode */ 152 153 /* HDLC Only */ 154 155 unsigned short flags; 156 unsigned char encoding; /* NRZ, NRZI, etc. */ 157 unsigned long clock_speed; /* external clock speed in bits per second */ 158 unsigned char addr_filter; /* receive HDLC address filter, 0xFF = disable */ 159 unsigned short crc_type; /* None, CRC16-CCITT, or CRC32-CCITT */ 160 unsigned char preamble_length; 161 unsigned char preamble; 162 163 /* Async Only */ 164 165 unsigned long data_rate; /* bits per second */ 166 unsigned char data_bits; /* 7 or 8 data bits */ 167 unsigned char stop_bits; /* 1 or 2 stop bits */ 168 unsigned char parity; /* none, even, or odd */ 169 170} MGSL_PARAMS, *PMGSL_PARAMS; 171 172#define MICROGATE_VENDOR_ID 0x13c0 173#define SYNCLINK_DEVICE_ID 0x0010 174#define MGSCC_DEVICE_ID 0x0020 175#define SYNCLINK_SCA_DEVICE_ID 0x0030 176#define SYNCLINK_GT_DEVICE_ID 0x0070 177#define SYNCLINK_GT4_DEVICE_ID 0x0080 178#define SYNCLINK_AC_DEVICE_ID 0x0090 179#define SYNCLINK_GT2_DEVICE_ID 0x00A0 180#define MGSL_MAX_SERIAL_NUMBER 30 181 182/* 183** device diagnostics status 184*/ 185 186#define DiagStatus_OK 0 187#define DiagStatus_AddressFailure 1 188#define DiagStatus_AddressConflict 2 189#define DiagStatus_IrqFailure 3 190#define DiagStatus_IrqConflict 4 191#define DiagStatus_DmaFailure 5 192#define DiagStatus_DmaConflict 6 193#define DiagStatus_PciAdapterNotFound 7 194#define DiagStatus_CantAssignPciResources 8 195#define DiagStatus_CantAssignPciMemAddr 9 196#define DiagStatus_CantAssignPciIoAddr 10 197#define DiagStatus_CantAssignPciIrq 11 198#define DiagStatus_MemoryError 12 199 200#define SerialSignal_DCD 0x01 /* Data Carrier Detect */ 201#define SerialSignal_TXD 0x02 /* Transmit Data */ 202#define SerialSignal_RI 0x04 /* Ring Indicator */ 203#define SerialSignal_RXD 0x08 /* Receive Data */ 204#define SerialSignal_CTS 0x10 /* Clear to Send */ 205#define SerialSignal_RTS 0x20 /* Request to Send */ 206#define SerialSignal_DSR 0x40 /* Data Set Ready */ 207#define SerialSignal_DTR 0x80 /* Data Terminal Ready */ 208 209 210/* 211 * Counters of the input lines (CTS, DSR, RI, CD) interrupts 212 */ 213struct mgsl_icount { 214 __u32 cts, dsr, rng, dcd, tx, rx; 215 __u32 frame, parity, overrun, brk; 216 __u32 buf_overrun; 217 __u32 txok; 218 __u32 txunder; 219 __u32 txabort; 220 __u32 txtimeout; 221 __u32 rxshort; 222 __u32 rxlong; 223 __u32 rxabort; 224 __u32 rxover; 225 __u32 rxcrc; 226 __u32 rxok; 227 __u32 exithunt; 228 __u32 rxidle; 229}; 230 231struct gpio_desc { 232 __u32 state; 233 __u32 smask; 234 __u32 dir; 235 __u32 dmask; 236}; 237 238#define DEBUG_LEVEL_DATA 1 239#define DEBUG_LEVEL_ERROR 2 240#define DEBUG_LEVEL_INFO 3 241#define DEBUG_LEVEL_BH 4 242#define DEBUG_LEVEL_ISR 5 243 244/* 245** Event bit flags for use with MgslWaitEvent 246*/ 247 248#define MgslEvent_DsrActive 0x0001 249#define MgslEvent_DsrInactive 0x0002 250#define MgslEvent_Dsr 0x0003 251#define MgslEvent_CtsActive 0x0004 252#define MgslEvent_CtsInactive 0x0008 253#define MgslEvent_Cts 0x000c 254#define MgslEvent_DcdActive 0x0010 255#define MgslEvent_DcdInactive 0x0020 256#define MgslEvent_Dcd 0x0030 257#define MgslEvent_RiActive 0x0040 258#define MgslEvent_RiInactive 0x0080 259#define MgslEvent_Ri 0x00c0 260#define MgslEvent_ExitHuntMode 0x0100 261#define MgslEvent_IdleReceived 0x0200 262 263/* Private IOCTL codes: 264 * 265 * MGSL_IOCSPARAMS set MGSL_PARAMS structure values 266 * MGSL_IOCGPARAMS get current MGSL_PARAMS structure values 267 * MGSL_IOCSTXIDLE set current transmit idle mode 268 * MGSL_IOCGTXIDLE get current transmit idle mode 269 * MGSL_IOCTXENABLE enable or disable transmitter 270 * MGSL_IOCRXENABLE enable or disable receiver 271 * MGSL_IOCTXABORT abort transmitting frame (HDLC) 272 * MGSL_IOCGSTATS return current statistics 273 * MGSL_IOCWAITEVENT wait for specified event to occur 274 * MGSL_LOOPTXDONE transmit in HDLC LoopMode done 275 * MGSL_IOCSIF set the serial interface type 276 * MGSL_IOCGIF get the serial interface type 277 */ 278#define MGSL_MAGIC_IOC 'm' 279#define MGSL_IOCSPARAMS _IOW(MGSL_MAGIC_IOC,0,struct _MGSL_PARAMS) 280#define MGSL_IOCGPARAMS _IOR(MGSL_MAGIC_IOC,1,struct _MGSL_PARAMS) 281#define MGSL_IOCSTXIDLE _IO(MGSL_MAGIC_IOC,2) 282#define MGSL_IOCGTXIDLE _IO(MGSL_MAGIC_IOC,3) 283#define MGSL_IOCTXENABLE _IO(MGSL_MAGIC_IOC,4) 284#define MGSL_IOCRXENABLE _IO(MGSL_MAGIC_IOC,5) 285#define MGSL_IOCTXABORT _IO(MGSL_MAGIC_IOC,6) 286#define MGSL_IOCGSTATS _IO(MGSL_MAGIC_IOC,7) 287#define MGSL_IOCWAITEVENT _IOWR(MGSL_MAGIC_IOC,8,int) 288#define MGSL_IOCCLRMODCOUNT _IO(MGSL_MAGIC_IOC,15) 289#define MGSL_IOCLOOPTXDONE _IO(MGSL_MAGIC_IOC,9) 290#define MGSL_IOCSIF _IO(MGSL_MAGIC_IOC,10) 291#define MGSL_IOCGIF _IO(MGSL_MAGIC_IOC,11) 292#define MGSL_IOCSGPIO _IOW(MGSL_MAGIC_IOC,16,struct gpio_desc) 293#define MGSL_IOCGGPIO _IOR(MGSL_MAGIC_IOC,17,struct gpio_desc) 294#define MGSL_IOCWAITGPIO _IOWR(MGSL_MAGIC_IOC,18,struct gpio_desc) 295#define MGSL_IOCSXSYNC _IO(MGSL_MAGIC_IOC, 19) 296#define MGSL_IOCGXSYNC _IO(MGSL_MAGIC_IOC, 20) 297#define MGSL_IOCSXCTRL _IO(MGSL_MAGIC_IOC, 21) 298#define MGSL_IOCGXCTRL _IO(MGSL_MAGIC_IOC, 22) 299 300 301#endif /* _UAPI_SYNCLINK_H_ */ 302