Searched refs:BIT4 (Results 1 - 25 of 40) sorted by relevance

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/linux-master/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h45 {0x0067, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0}, /*0x67[0] = 0 to disable BT_GPS_SEL pins*/ \
48 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \
54 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0},/* disable WL suspend*/ \
83 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT3)}, /*0x04[12:11] = 2b'11 enable WL suspend for PCIe*/ \
84 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3}, /*0x04[12:11] = 2b'01 enable WL suspend*/ \
85 {0x0023, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, BIT4}, /*0x23[4] = 1b'1 12H LDO enter sleep mode*/ \
87 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3|BIT4, BIT3|BIT4}, /*
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H A Drtl8723b_spec.h210 #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */
H A Dosdep_service.h21 #define BIT4 0x00000010 macro
H A Dhal_com_reg.h551 #define RRSR_6M BIT4
576 #define HAL92C_WOL_FW_DISCONNECT_EVENT BIT4
711 #define IMR_BKDOK BIT4 /* AC_BK DMA OK Interrupt */
759 #define RCR_ADD3 BIT4 /* Accept address 3 match packet */
1282 #define SDIO_HIMR_TXFOVW_MSK BIT4
1304 #define SDIO_HISR_TXFOVW BIT4
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h99 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
161 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x10, BIT4 \
279 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
375 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4, 0 \
386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \
404 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3), 0 \
416 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT5|BIT4), (BIT5|BIT4) \
475 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT4|BIT3, (BIT4|BIT
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/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h35 #define BIT4 0x00000010 macro
H A Dhalbtc8821a2ant.h11 #define BT_INFO_8821A_2ANT_B_SCO_BUSY BIT4
H A Dhalbtc8723b1ant.h10 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
H A Dhalbtc8723b2ant.h13 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
H A Dhalbtc8821a1ant.h11 #define BT_INFO_8821A_1ANT_B_SCO_BUSY BIT4
H A Dhalbtc8192e2ant.h10 #define BT_INFO_8192E_2ANT_B_SCO_BUSY BIT4
H A Dhalbtcoutsrc.h96 #define ALGO_TRACE_FW BIT4
108 #define WIFI_P2P_GC_CONNECTED BIT4
/linux-master/drivers/scsi/
H A Ddc395x.h72 #define BIT4 0x00000010 macro
133 #define PARITY_ERROR BIT4
140 #define ENABLE_TIMER BIT4
169 #define WIDE_NEGO_STATE BIT4
596 #define NO_SEEK BIT4
/linux-master/drivers/staging/rtl8723bs/hal/
H A DHalBtc8723b2Ant.h11 #define BT_INFO_8723B_2ANT_B_SCO_BUSY BIT4
H A DHalBtc8723b1Ant.h11 #define BT_INFO_8723B_1ANT_B_SCO_BUSY BIT4
H A DHalHWImg8723B_MAC.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */
H A DHal8723BReg.h399 #define IMR_BEDOK_8723B BIT4 /* AC_BE DMA OK */
H A DHalHWImg8723B_RF.c16 ((pDM_Odm->BoardType & BIT4) >> 4) << 0 | /* _GLNA */
H A DHalBtcOutSrc.h76 #define WIFI_P2P_GC_CONNECTED BIT4
/linux-master/drivers/video/fbdev/via/
H A Ddvi.c61 viafb_write_reg_mask(SR1E, VIASR, 0xF0, BIT4 +
326 viafb_write_reg_mask(SR2A, VIASR, 0, BIT4);
347 viafb_write_reg_mask(SR2A, VIASR, 0x10, BIT4);
H A Dshare.h18 #define BIT4 0x10 macro
H A Dhw.c947 viafb_write_reg_mask(CR35, VIACR, 0x10, BIT4);
1713 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
1717 viafb_write_reg_mask(CRD2, VIACR, 0x10, BIT4 + BIT5);
1720 viafb_write_reg_mask(CRD2, VIACR, 0x30, BIT4 + BIT5);
1725 viafb_write_reg_mask(CRD2, VIACR, 0x20, BIT4 + BIT5);
1728 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT4 + BIT5);
2061 BIT4);
/linux-master/include/uapi/linux/
H A Dsynclink.h23 #define BIT4 0x0010 macro
/linux-master/lib/zstd/common/
H A Dzstd_internal.h69 #define BIT4 16 macro
/linux-master/drivers/tty/
H A Dsynclink_gt.c353 #define MASK_OVERRUN BIT4
391 #define IRQ_RI BIT4
2133 if (status & (BIT5 + BIT4)) {
2158 if (status & (BIT5 + BIT4 + BIT3)) {
4038 case 6: val |= BIT4; break;
4040 case 8: val |= BIT5 + BIT4; break;
4078 case 6: val |= BIT4; break;
4080 case 8: val |= BIT5 + BIT4; break;
4204 case HDLC_PREAMBLE_LENGTH_32BITS: val |= BIT4; break;
4205 case HDLC_PREAMBLE_LENGTH_64BITS: val |= BIT5 + BIT4; brea
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