/linux-master/drivers/staging/rtl8723bs/include/ |
H A D | rtw_ht.h | 66 #define LDPC_HT_TEST_TX_ENABLE BIT2 71 #define STBC_HT_TEST_TX_ENABLE BIT2 76 #define BEAMFORMING_HT_BEAMFORMER_TEST BIT2 /* Transmiting Beamforming no matter the target supports it or not */
|
H A D | hal_pwr_seq.h | 48 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0},/* disable SW LPS 0x04[10]= 0 and WLSUS_EN 0x04[11]= 0*/ \ 105 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2}, /*0x04[10] = 1, enable SW LPS*/ \ 183 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/*Reset CPU*/ \ 208 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0},/* Enable CPU*/ \ 210 {0x0003, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2},/* Enable CPU*/ \
|
H A D | rtl8723b_spec.h | 212 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
|
H A D | osdep_service.h | 19 #define BIT2 0x00000004 macro
|
H A D | hal_com_reg.h | 549 #define RRSR_5_5M BIT2 574 #define HAL92C_WOL_DISASSOC_EVENT BIT2 639 #define BW_OPMODE_20MHZ BIT2 672 #define WOW_MAGIC BIT2 /* Magic packet */ 713 #define IMR_VIDOK BIT2 /* AC_VI DMA OK Interrupt */ 761 #define RCR_AM BIT2 /* Accept multicast packet */ 1280 #define SDIO_HIMR_TXERR_MSK BIT2 1302 #define SDIO_HISR_TXERR BIT2 1375 #define WL_FUNC_EN BIT2 /* WiFi function enable */
|
/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
H A D | halbt_precomp.h | 33 #define BIT2 0x00000004 macro
|
H A D | halbtc8821a2ant.h | 13 #define BT_INFO_8821A_2ANT_B_INQ_PAGE BIT2
|
H A D | halbtc8723b1ant.h | 12 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
|
H A D | halbtc8723b2ant.h | 15 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
|
H A D | halbtc8821a1ant.h | 13 #define BT_INFO_8821A_1ANT_B_INQ_PAGE BIT2
|
H A D | halbtc8192e2ant.h | 12 #define BT_INFO_8192E_2ANT_B_INQ_PAGE BIT2
|
H A D | halbtcoutsrc.h | 89 #define INTF_NOTIFY BIT2 94 #define ALGO_BT_MONITOR BIT2 106 #define WIFI_HS_CONNECTED BIT2
|
/linux-master/drivers/scsi/ |
H A D | dc395x.h | 74 #define BIT2 0x00000004 macro 81 #define FORMATING_MEDIA BIT2 87 #define ASPI_SUPPORT BIT2 123 #define RESET_DONE BIT2 131 #define OVER_RUN BIT2 141 #define RESET_DEV0 BIT2 167 #define WIDE_NEGO_ENABLE BIT2 594 #define RST_SCSI_BUS BIT2
|
/linux-master/drivers/video/fbdev/via/ |
H A D | dvi.c | 335 BIT0 + BIT1 + BIT2); 338 BIT0 + BIT1 + BIT2); 345 BIT0 + BIT1 + BIT2 + BIT3); 370 BIT0 + BIT1 + BIT2 + BIT3); 377 BIT0 + BIT1 + BIT2 + BIT3);
|
H A D | share.h | 16 #define BIT2 0x04 macro
|
H A D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2); 520 BIT0 + BIT1 + BIT2 + BIT3); 561 BIT0 + BIT1 + BIT2); 744 BIT7 + BIT2 + BIT1 + BIT0);
|
/linux-master/drivers/staging/rtl8723bs/hal/ |
H A D | HalBtc8723b2Ant.h | 13 #define BT_INFO_8723B_2ANT_B_INQ_PAGE BIT2
|
H A D | HalHWImg8723B_MAC.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ 60 if ((cond1 & BIT2) != 0) /* ALNA */
|
H A D | HalBtc8723b1Ant.h | 13 #define BT_INFO_8723B_1ANT_B_INQ_PAGE BIT2
|
H A D | HalHWImg8723B_RF.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ 66 if ((cond1 & BIT2) != 0) /* ALNA */
|
H A D | HalHWImg8723B_BB.c | 20 ((pDM_Odm->BoardType & BIT2) >> 2) << 4; /* _BT */ 61 if ((cond1 & BIT2) != 0) /* ALNA */
|
H A D | Hal8723BReg.h | 401 #define IMR_VODOK_8723B BIT2 /* AC_VO DMA OK */
|
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
H A D | pwrseq.h | 26 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ 130 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ 199 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, 0 \ 205 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \ 386 PWR_BASEADDR_MAC, PWR_CMD_WRITE, (BIT4|BIT3|BIT2), 0 \ 523 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT2, BIT2 \
|
/linux-master/include/uapi/linux/ |
H A D | synclink.h | 21 #define BIT2 0x0004 macro
|
/linux-master/drivers/tty/ |
H A D | synclink_gt.c | 191 #define desc_eof(a) (le16_to_cpu((a).status) & BIT2) 1933 if (status & BIT2) { 2203 wr_reg16(info, TCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3802 /* SCR (serial control) BIT2=loopback enable */ 3803 wr_reg16(info, SCR, (unsigned short)(rd_reg16(info, SCR) | BIT2)); 3852 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3877 wr_reg16(info, RCR, (unsigned short)(val | BIT2)); /* set reset bit */ 3899 wr_reg32(info, RDCSR, (BIT2 + BIT0)); 3902 wr_reg32(info, RDCSR, (BIT6 + BIT2 + BIT0)); 3919 (unsigned short)((rd_reg16(info, TCR) | BIT1) & ~BIT2)); [all...] |