Searched refs:BIT12 (Results 1 - 13 of 13) sorted by relevance

/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h43 #define BIT12 0x00001000 macro
/linux-master/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h203 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */
H A Dosdep_service.h29 #define BIT12 0x00001000 macro
H A Dhal_com_reg.h559 #define RRSR_MCS0 BIT12
703 #define IMR_RXFOVW BIT12 /* Receive FIFO Overflow */
719 #define IMR_BcnInt_E BIT12
750 #define RCR_ACF BIT12 /* Accept control type frame. Control frames BA, BAR, and PS-Poll (when in AP mode) are not controlled by this bit. They are controlled by ADF. */
H A Drtw_mlme_ext.h56 #define DYNAMIC_BB_RXHP BIT12/* ODM_BB_RXHP */
/linux-master/include/uapi/linux/
H A Dsynclink.h31 #define BIT12 0x1000 macro
/linux-master/drivers/scsi/
H A Ddc395x.h64 #define BIT12 0x00001000 macro
/linux-master/drivers/staging/rtl8723bs/hal/
H A DHal8723BReg.h392 #define IMR_ATIMEND_8723B BIT12 /* CTWidnow End or ATIM Window End */
H A Dodm.h377 ODM_BB_RXHP = BIT12,
H A Dodm_DIG.c665 PHY_SetBBReg(pDM_Odm->Adapter, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
/linux-master/drivers/tty/
H A Dsynclink_gt.c382 #define IRQ_TXIDLE BIT12
4186 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4187 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4188 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4189 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
4259 case HDLC_ENCODING_BIPHASE_MARK: val |= BIT12; break;
4260 case HDLC_ENCODING_BIPHASE_SPACE: val |= BIT12 + BIT10; break;
4261 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break;
4262 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break;
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8192de/
H A Dreg.h370 #define RRSR_MCS0 BIT12
/linux-master/drivers/scsi/lpfc/
H A Dlpfc_hw4.h779 #define LPFC_SLI4_INTR12 BIT12

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