| /linux-master/drivers/staging/rtl8723bs/include/ |
| H A D | hal_pwr_seq.h | 50 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1},/* wait till 0x04[17] = 1 power ready*/ \
58 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable falling edge triggering interrupt*/\
59 {0x0063, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable GPIO9 interrupt mode*/\
60 {0x0062, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0},/*Enable GPIO9 input mode*/\
62 {0x005A, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1},/*Enable HSISR GPIO9 interrupt*/\
71 {0x0049, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1,
[all...] |
| H A D | rtw_ht.h | 65 #define LDPC_HT_ENABLE_TX BIT1
70 #define STBC_HT_ENABLE_TX BIT1
75 #define BEAMFORMING_HT_BEAMFORMEE_ENABLE BIT1 /* Declare our NIC supports beamformee */
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| H A D | hal_phy.h | 14 #define ANT_DETECT_BY_RSSI BIT1
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| H A D | hal_com_reg.h | 548 #define RRSR_2M BIT1
573 #define HAL92C_WOL_GTK_UPDATE_EVENT BIT1
671 #define WOW_WOMEN BIT1 /* WoW function on or off. */
714 #define IMR_VODOK BIT1 /* AC_VO DMA Interrupt */
725 #define IMR_OCPINT BIT1
762 #define RCR_APM BIT1 /* Accept physical match packet */
1279 #define SDIO_HIMR_AVAL_MSK BIT1
1301 #define SDIO_HISR_AVAL BIT1
1337 #define HCI_RESUME_PWR_RDY BIT1
1374 #define WL_HWPDN_SL BIT1 /* WiF
[all...] |
| H A D | rtl8723b_spec.h | 213 #define IMR_RDU_8723B BIT1 /* Rx Descriptor Unavailable */
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| H A D | osdep_service.h | 18 #define BIT1 0x00000002 macro
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| H A D | rtw_pwrctrl.h | 125 #define RT_PCI_ASPM_OSC_DISABLE BIT1 /* PCI ASPM controlled by driver or BIOS, i.e., force enable ASPM */
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| /linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| H A D | pwrseq.h | 29 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, BIT1 \
57 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
66 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, BIT1 \
69 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT1, 0 \
170 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
173 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
253 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1, 0 \
259 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1,
[all...] |
| /linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 32 #define BIT1 0x00000002 macro
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| H A D | halbtc8821a2ant.h | 14 #define BT_INFO_8821A_2ANT_B_SCO_ESCO BIT1
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| H A D | halbtc8723b1ant.h | 13 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
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| H A D | halbtc8723b2ant.h | 16 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
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| H A D | halbtc8821a1ant.h | 14 #define BT_INFO_8821A_1ANT_B_SCO_ESCO BIT1
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| H A D | halbtc8192e2ant.h | 13 #define BT_INFO_8192E_2ANT_B_SCO_ESCO BIT1
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| /linux-master/drivers/scsi/ |
| H A D | dc395x.h | 75 #define BIT1 0x00000002 macro
80 #define UNIT_INFO_CHANGED BIT1
86 #define SCSI_SUPPORT BIT1
122 #define RESET_DETECT BIT1
130 #define ABORTION BIT1
142 #define ABORT_DEV BIT1
166 #define SYNC_NEGO_DONE BIT1
593 #define GREATER_1G BIT1
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| /linux-master/drivers/video/fbdev/via/ |
| H A D | dvi.c | 45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
325 viafb_write_reg_mask(SR1B, VIASR, 0, BIT1);
335 BIT0 + BIT1 + BIT2);
338 BIT0 + BIT1 + BIT2);
345 BIT0 + BIT1 + BIT2 + BIT3);
346 viafb_write_reg_mask(SR1B, VIASR, 0x02, BIT1);
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
370 BIT0 + BIT1 + BIT2 + BIT3);
377 BIT0 + BIT1
[all...] |
| H A D | lcd.c | 345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
520 BIT0 + BIT1 + BIT2 + BIT3);
561 BIT0 + BIT1 + BIT2);
606 viafb_write_reg_mask(CRD4, VIACR, 0, BIT1);
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
672 viafb_write_reg_mask(CRD4, VIACR, 0x02, BIT1);
744 BIT7 + BIT2 + BIT1 + BIT0);
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| H A D | via_utility.c | 170 viafb_write_reg_mask(CR6A, VIACR, 0x02, BIT1);
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| H A D | share.h | 15 #define BIT1 0x02 macro
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| /linux-master/drivers/staging/rtl8723bs/hal/ |
| H A D | HalBtc8723b2Ant.h | 14 #define BT_INFO_8723B_2ANT_B_SCO_ESCO BIT1
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| H A D | odm_DIG.h | 82 ODM_RESUME_DIG = BIT1
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| H A D | HalBtc8723b1Ant.h | 14 #define BT_INFO_8723B_1ANT_B_SCO_ESCO BIT1
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| H A D | HalHWImg8723B_MAC.c | 58 if ((cond1 & BIT1) != 0) /* GPA */
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| /linux-master/include/uapi/linux/ |
| H A D | synclink.h | 20 #define BIT1 0x0002 macro
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| /linux-master/lib/zstd/common/ |
| H A D | zstd_internal.h | 70 #define BIT1 2 macro
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