Searched refs:BIT0 (Results 1 - 25 of 52) sorted by relevance

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/linux-master/drivers/staging/rtl8723bs/include/
H A Dhal_pwr_seq.h44 {0x0020, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_USB_MSK|PWR_INTF_SDIO_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0}, /*0x20[0] = 1b'1 enable LDOA12 MACRO block for all interface*/ \
49 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* Disable USB suspend */ \
51 {0x0075, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_PCI_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0},/* Enable USB suspend */ \
52 {0x0006, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* release WLON reset 0x04[16]= 1*/ \
55 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0},/* polling until return 0*/ \
56 {0x0005, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK, PWR_INTF_ALL_MSK, PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0,
[all...]
H A Drtw_ht.h64 #define LDPC_HT_ENABLE_RX BIT0
69 #define STBC_HT_ENABLE_RX BIT0
74 #define BEAMFORMING_HT_BEAMFORMER_ENABLE BIT0 /* Declare our NIC supports beamformer */
H A Dhal_phy.h13 #define ANT_DETECT_BY_SINGLE_TONE BIT0
H A Dhal_com_reg.h524 #define HSISR_GPIO12_0_INT BIT0
547 #define RRSR_1M BIT0
572 #define HAL92C_WOL_PTK_UPDATE_EVENT BIT0
670 #define WOW_PMEN BIT0 /* Power management Enable. */
715 #define IMR_ROK BIT0 /* Receive DMA OK Interrupt */
726 #define IMR_WLANOFF BIT0
763 #define RCR_AAP BIT0 /* Accept all unicast packet */
1278 #define SDIO_HIMR_RX_REQUEST_MSK BIT0
1300 #define SDIO_HISR_RX_REQUEST BIT0
1338 #define HCI_SUS_CTRL BIT0
[all...]
H A Drtl8723b_spec.h214 #define IMR_ROK_8723B BIT0 /* Receive DMA OK */
H A Dosdep_service.h17 #define BIT0 0x00000001 macro
/linux-master/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/
H A Dpwrseq.h38 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
41 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT0, 0},
51 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
96 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
155 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x01, BIT0 \
181 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, BIT0 \
247 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT0, 0 \
294 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT1|BIT0, BIT
[all...]
/linux-master/drivers/video/fbdev/via/
H A Ddvi.c45 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
52 viafb_write_reg_mask(SR2A, VIASR, 0x03, BIT0 + BIT1);
335 BIT0 + BIT1 + BIT2);
338 BIT0 + BIT1 + BIT2);
345 BIT0 + BIT1 + BIT2 + BIT3);
363 viafb_write_reg_mask(CR99, VIACR, 0x03, BIT0 + BIT1);
370 BIT0 + BIT1 + BIT2 + BIT3);
377 BIT0 + BIT1 + BIT2 + BIT3);
395 viafb_write_reg_mask(CR6B, VIACR, 0x01, BIT0);
396 viafb_write_reg_mask(CR6C, VIACR, 0x21, BIT0
[all...]
H A Dvia_utility.c152 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
169 viafb_write_reg_mask(SR1A, VIASR, 0x01, BIT0);
207 viafb_write_reg_mask(SR1A, VIASR, 0x0, BIT0);
H A Dlcd.c345 viafb_write_reg_mask(CR79, VIACR, 0x07, BIT0 + BIT1 + BIT2);
520 BIT0 + BIT1 + BIT2 + BIT3);
561 BIT0 + BIT1 + BIT2);
583 viafb_write_reg_mask(CR6A, VIACR, 0x01, BIT0);
650 viafb_write_reg_mask(CRD2, VIACR, 0x00, BIT0 + BIT1);
652 viafb_write_reg_mask(CRD2, VIACR, 0x03, BIT0 + BIT1);
659 viafb_write_reg_mask(CR91, VIACR, 0, BIT0);
668 viafb_write_reg_mask(CRD3, VIACR, 0, BIT0);
744 BIT7 + BIT2 + BIT1 + BIT0);
844 bdithering = BIT0;
[all...]
/linux-master/drivers/scsi/
H A Ddc395x.h76 #define BIT0 0x00000001 macro
79 #define UNIT_ALLOCATED BIT0
85 #define DASD_SUPPORT BIT0
121 #define RESET_DEV BIT0
126 #define ABORT_DEV_ BIT0
129 #define SRB_OK BIT0
143 #define AUTO_REQSENSE BIT0
165 #define SYNC_NEGO_ENABLE BIT0
592 #define MORE2_DRV BIT0
/linux-master/drivers/net/wireless/realtek/rtlwifi/btcoexist/
H A Dhalbt_precomp.h31 #define BIT0 0x00000001 macro
H A Dhalbtc8723b1ant.h14 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
17 (((_BT_INFO_EXT_&BIT0)) ? true : false)
H A Dhalbtc8821a1ant.h15 #define BT_INFO_8821A_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_&BIT0)) ? true : false)
H A Dhalbtc8821a2ant.h15 #define BT_INFO_8821A_2ANT_B_CONNECTION BIT0
H A Dhalbtc8723b2ant.h17 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
H A Dhalbtc8192e2ant.h14 #define BT_INFO_8192E_2ANT_B_CONNECTION BIT0
H A Dhalbtcoutsrc.h88 #define INTF_INIT BIT0
92 #define ALGO_BT_RSSI_STATE BIT0
104 #define WIFI_STA_CONNECTED BIT0
/linux-master/drivers/staging/rtl8723bs/hal/
H A Dodm_reg.h89 #define BIT_FA_RESET BIT0
H A DHalBtc8723b1Ant.h15 #define BT_INFO_8723B_1ANT_B_CONNECTION BIT0
18 (((_BT_INFO_EXT_ & BIT0)) ? true : false)
H A DHalBtc8723b2Ant.h15 #define BT_INFO_8723B_2ANT_B_CONNECTION BIT0
H A Dodm_DIG.h81 ODM_PAUSE_DIG = BIT0,
H A Dodm_HWConfig.c338 pEntry->rssi_stat.PacketMap = (pEntry->rssi_stat.PacketMap<<1) | BIT0;
372 OFDM_pkt += (u8)(pEntry->rssi_stat.PacketMap>>i)&BIT0;
/linux-master/drivers/tty/
H A Dsynclink_gt.c186 #define set_desc_eof(a,b) (a).status = cpu_to_le16((b) ? (le16_to_cpu((a).status) | BIT0) : (le16_to_cpu((a).status) & ~BIT0))
193 #define desc_abort(a) (le16_to_cpu((a).status) & BIT0)
351 #define MASK_FRAMING BIT0
393 #define IRQ_MASTER BIT0
1781 status = *(p + 1) & (BIT1 + BIT0);
1785 else if (status & BIT0)
1792 else if (status & BIT0)
2005 if (status & BIT0) {
3778 if (!(rd_reg32(info, RDCSR) & BIT0))
[all...]
/linux-master/include/uapi/linux/
H A Dsynclink.h19 #define BIT0 0x0001 macro

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