Searched refs:AR71XX_RESET_REG_MISC_INT_ENABLE (Results 1 - 3 of 3) sorted by last modified time

/linux-master/arch/mips/include/asm/mach-ath79/
H A Dar71xx_regs.h517 #define AR71XX_RESET_REG_MISC_INT_ENABLE 0x14 macro
/linux-master/drivers/irqchip/
H A Dirq-ath79-misc.c19 #define AR71XX_RESET_REG_MISC_INT_ENABLE 4 macro
42 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
66 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
67 __raw_writel(t | BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE);
70 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
79 t = __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
80 __raw_writel(t & ~BIT(irq), base + AR71XX_RESET_REG_MISC_INT_ENABLE); local
83 __raw_readl(base + AR71XX_RESET_REG_MISC_INT_ENABLE);
125 __raw_writel(0, base + AR71XX_RESET_REG_MISC_INT_ENABLE);
/linux-master/arch/mips/ath79/
H A Dclock.c532 misc = ath79_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE);
534 ath79_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE, misc);

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