Searched refs:AMDGPU_TILING_GET (Results 1 - 9 of 9) sorted by relevance
/linux-master/drivers/gpu/drm/amd/display/amdgpu_dm/ |
H A D | amdgpu_dm_plane.c | 184 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == DC_ARRAY_2D_TILED_THIN1) { 187 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 188 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 189 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 190 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 191 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 203 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) 209 AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
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H A D | amdgpu_dm.c | 10214 linear = AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_2D_TILED_THIN1 && 10215 AMDGPU_TILING_GET(afb->tiling_flags, ARRAY_MODE) != DC_ARRAY_1D_TILED_THIN1 && 10216 AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE) == 0; 10218 linear = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0;
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/linux-master/drivers/gpu/drm/amd/amdgpu/ |
H A D | amdgpu_display.c | 731 if (!afb->tiling_flags || !AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) { 734 int swizzle = AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE); 743 uint32_t dcc_offset = AMDGPU_TILING_GET(afb->tiling_flags, DCC_OFFSET_256B); 829 AMD_FMT_MOD_SET(TILE, AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE)) | 836 bool dcc_i64b = AMDGPU_TILING_GET(afb->tiling_flags, DCC_INDEPENDENT_64B) != 0; 861 AMDGPU_TILING_GET(afb->tiling_flags, DCC_PITCH_MAX) + 1; 921 if (AMDGPU_TILING_GET(afb->tiling_flags, SWIZZLE_MODE) == 0) 924 micro_tile_mode = AMDGPU_TILING_GET(afb->tiling_flags, MICRO_TILE_MODE);
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H A D | dce_v11_0.c | 1945 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 2035 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 2038 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 2039 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 2040 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 2041 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 2042 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2055 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
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H A D | dce_v10_0.c | 1895 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1985 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1988 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1989 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1990 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1991 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1992 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 2005 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
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H A D | dce_v8_0.c | 1842 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG); 1924 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1927 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1928 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1929 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1930 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1931 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1940 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
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H A D | dce_v6_0.c | 1955 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) { 1958 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH); 1959 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT); 1960 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT); 1961 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); 1962 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS); 1970 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) { 1974 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
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H A D | amdgpu_object.c | 1126 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
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/linux-master/include/uapi/drm/ |
H A D | amdgpu_drm.h | 412 #define AMDGPU_TILING_GET(value, field) \ macro
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