Searched refs:x86 (Results 1 - 25 of 116) sorted by relevance

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/u-boot/include/configs/
H A Dchromebox_panther.h9 #include <configs/x86-common.h>
10 #include <configs/x86-chromebook.h>
H A Dchromebook_link.h15 #include <configs/x86-common.h>
16 #include <configs/x86-chromebook.h>
H A Dchromebook_samus.h15 #include <configs/x86-common.h>
16 #include <configs/x86-chromebook.h>
H A Dchromebook_coral.h13 #include <configs/x86-common.h>
14 #include <configs/x86-chromebook.h>
H A Dsom-db5800-som-6867.h13 #include <configs/x86-common.h>
H A Dtheadorable-x86-conga-qa3-e3845.h13 #include <configs/x86-common.h>
16 #define DEF_ENV_TFTPDIR "theadorable-x86-conga"
24 * Include the theadorable-x86 common options, macros and default
27 #include <configs/theadorable-x86-common.h>
H A Dtheadorable-x86-dfi-bt700.h13 #include <configs/x86-common.h>
18 #define DEF_ENV_TFTPDIR "theadorable-x86-dfi"
26 * Include the theadorable-x86 common options, macros and default
29 #include <configs/theadorable-x86-common.h>
H A Dconga-qeval20-qa3-e3845.h13 #include <configs/x86-common.h>
H A Ddfi-bt700.h13 #include <configs/x86-common.h>
/u-boot/drivers/bios_emulator/
H A Dbios.c77 if (M.x86.R_AH == 0x12 && M.x86.R_BL == 0x32) {
78 if (M.x86.R_AL == 0) {
82 } else if (M.x86.R_AL == 1) {
90 M.x86.R_AL);
97 M.x86.R_AH, M.x86.R_AL, M.x86.R_BL);
126 #define DEVICE_NOT_FOUND 0x86
162 switch (M.x86
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H A Dbiosemu.c110 M.x86.debug = debugFlags;
184 NOTE: The memory is *always* in little endian format, son on non-x86
212 NOTE: The memory is *always* in little endian format, son on non-x86
243 and loads all the x86 registers from the passed in registers structure.
249 M.x86.R_EAX = regs->e.eax;
250 M.x86.R_EBX = regs->e.ebx;
251 M.x86.R_ECX = regs->e.ecx;
252 M.x86.R_EDX = regs->e.edx;
253 M.x86.R_ESI = regs->e.esi;
254 M.x86
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/u-boot/drivers/bios_emulator/x86emu/
H A Ddecode.c53 if (M.x86.intr & INTR_SYNCH) {
54 intno = M.x86.intno;
58 push_word((u16)M.x86.R_FLG);
61 push_word(M.x86.R_CS);
62 M.x86.R_CS = mem_access_word(intno * 4 + 2);
63 push_word(M.x86.R_IP);
64 M.x86.R_IP = mem_access_word(intno * 4);
65 M.x86.intr = 0;
81 M.x86.intno = intrnum;
82 M.x86
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H A Ddebug.c61 printk("%04x:%04x ", M.x86.saved_cs, M.x86.saved_ip);
62 print_encoded_bytes(M.x86.saved_cs, M.x86.saved_ip);
80 printk("%04x:%04x ", M.x86.saved_cs, M.x86.saved_ip);
81 print_encoded_bytes(M.x86.saved_cs, M.x86.saved_ip);
115 tregs.x86.R_IP = off;
116 tregs.x86
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H A Dops.c38 * and emulation of all the x86 processor instructions.
182 if (M.x86.R_SP != 0) {
186 M.x86.R_CS, M.x86.R_IP-1,op1));
259 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
283 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
362 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
378 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
416 M.x86.R_AL = genop_byte_operation[op1](M.x86
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H A Dprim_ops.c1207 /* was (M.x86.R_FLG&F_CF)==F_CF)), */
1876 s16 res = (s16)((s8)M.x86.R_AL * (s8)s);
1878 M.x86.R_AX = res;
1879 if (((M.x86.R_AL & 0x80) == 0 && M.x86.R_AH == 0x00) ||
1880 ((M.x86.R_AL & 0x80) != 0 && M.x86.R_AH == 0xFF)) {
1895 s32 res = (s16)M.x86.R_AX * (s16)s;
1897 M.x86.R_AX = (u16)res;
1898 M.x86
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H A Dops2.c39 * and emulation of all the x86 extended two-byte processor
65 M.x86.R_CS, M.x86.R_IP-2,op2);
155 target += (s16) M.x86.R_IP;
159 M.x86.R_IP = (u16)target;
269 push_word(M.x86.R_FS);
283 M.x86.R_FS = pop_word();
303 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
327 if (M.x86.mode & SYSMODE_PREFIX_DATA) {
366 if (M.x86
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H A Dsys.c322 push_word((u16) M.x86.R_FLG);
325 push_word(M.x86.R_CS);
326 M.x86.R_CS = mem_access_word(num * 4 + 2);
327 push_word(M.x86.R_IP);
328 M.x86.R_IP = mem_access_word(num * 4);
329 M.x86.intr = 0;
/u-boot/arch/x86/lib/
H A Dbios_interrupts.c29 switch ((M.x86.R_EAX & 0xff00) >> 8) {
34 if (cursor_row != ((M.x86.R_EDX >> 8) & 0xff) ||
35 cursor_col >= (M.x86.R_EDX & 0xff)) {
38 cursor_row = (M.x86.R_EDX >> 8) & 0xff;
39 cursor_col = M.x86.R_EDX & 0xff;
43 M.x86.R_EAX &= 0x00ff;
44 M.x86.R_ECX = 0x0607;
45 M.x86.R_EDX = (cursor_row << 8) | cursor_col;
53 M.x86.R_EAX = 0x0f00 | 'A'; /* White on black 'A' */
58 debug("%c", M.x86
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H A Dbios.c3 * From Coreboot file device/oprom/realmode/x86.c
65 .eax = M.x86.R_EAX,
66 .ecx = M.x86.R_ECX,
67 .edx = M.x86.R_EDX,
68 .ebx = M.x86.R_EBX,
69 .esp = M.x86.R_ESP,
70 .ebp = M.x86.R_EBP,
71 .esi = M.x86.R_ESI,
72 .edi = M.x86.R_EDI,
73 .vector = M.x86
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H A Dcmd_boot.c21 #include <asm/u-boot-x86.h>
32 * x86 does not use a dedicated register to pass the pointer to
/u-boot/arch/x86/include/asm/
H A Du-boot.h24 #include <asm/u-boot-x86.h>
/u-boot/arch/x86/
H A DMakefile5 head-y := arch/x86/cpu/start64.o
8 head-y := arch/x86/cpu/start.o
11 head-y := arch/x86/cpu/start.o
14 head-y = arch/x86/cpu/start_from_tpl.o
16 head-y = arch/x86/cpu/start_from_spl.o
23 head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o
24 head-$(CONFIG_$(SPL_TPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o
26 libs-y += arch/x86/cpu/
27 libs-y += arch/x86/lib/
/u-boot/drivers/bios_emulator/include/x86emu/
H A Ddebug.h53 # define CHECK_IP_FETCH() (M.x86.check & CHECK_IP_FETCH_F)
54 # define CHECK_SP_ACCESS() (M.x86.check & CHECK_SP_ACCESS_F)
55 # define CHECK_MEM_ACCESS() (M.x86.check & CHECK_MEM_ACCESS_F)
56 # define CHECK_DATA_ACCESS() (M.x86.check & CHECK_DATA_ACCESS_F)
65 # define DEBUG_INSTRUMENT() (M.x86.debug & DEBUG_INSTRUMENT_F)
66 # define DEBUG_DECODE() (M.x86.debug & DEBUG_DECODE_F)
67 # define DEBUG_TRACE() (M.x86.debug & DEBUG_TRACE_F)
68 # define DEBUG_STEP() (M.x86.debug & DEBUG_STEP_F)
69 # define DEBUG_DISASSEMBLE() (M.x86.debug & DEBUG_DISASSEMBLE_F)
70 # define DEBUG_BREAK() (M.x86
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/u-boot/arch/x86/cpu/tangier/
H A Dtangier.c9 #include <asm/u-boot-x86.h>
/u-boot/arch/x86/cpu/efi/
H A Dsdram.c10 #include <asm/u-boot-x86.h>

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