| /u-boot/drivers/clk/ |
| H A D | clk-hsdk-cgu.c | 424 static ulong pll_get(struct clk *sclk) argument
429 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
457 static unsigned long hsdk_pll_round_rate(struct clk *sclk, unsigned long rate) argument
461 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
533 static ulong pll_set(struct clk *sclk, ulong rate) argument
537 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
541 best_rate = hsdk_pll_round_rate(sclk, rate);
553 static int idiv_off(struct clk *sclk) argument
555 struct hsdk_cgu_clk *clk = dev_get_priv(sclk->dev);
562 static ulong idiv_get(struct clk *sclk) argument
579 cpu_clk_set(struct clk *sclk, ulong rate) argument
594 common_div_clk_set(struct clk *sclk, ulong rate, const struct hsdk_div_full_cfg *cfg) argument
637 axi_clk_set(struct clk *sclk, ulong rate) argument
642 tun_hsdk_set(struct clk *sclk, ulong rate) argument
647 tun_h4xd_set(struct clk *sclk, ulong rate) argument
652 idiv_set(struct clk *sclk, ulong rate) argument
683 hsdk_prepare_clock_tree_branch(struct clk *sclk) argument
702 hsdk_cgu_get_rate(struct clk *sclk) argument
712 hsdk_cgu_set_rate(struct clk *sclk, ulong rate) argument
725 hsdk_cgu_disable(struct clk *sclk) argument
[all...] |
| /u-boot/drivers/mmc/ |
| H A D | ftsdc010_mci.h | 17 uint32_t sclk; /* FTSDC010 source clock in Hz */ member in struct:ftsdc010_chip
|
| H A D | exynos_dw_mmc.c | 64 unsigned long sclk; local
75 sclk = get_mmc_clk(host->dev_index);
81 return sclk / clk_div / (host->div + 1);
106 unsigned long freq, sclk; local
114 sclk = get_mmc_clk(host->dev_index);
115 div = DIV_ROUND_UP(sclk, freq);
|
| H A D | mtk-sd.c | 371 u32 sclk; /* actual calculated bus clock */ member in struct:msdc_host
804 if (host->sclk == 0) {
807 clk_ns = 1000000000UL / host->sclk;
809 /* unit is 1048576 sclk cycles */
854 u32 sclk; local
878 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */
882 sclk = (host->src_clk_freq >> 2) / div;
894 sclk = host->src_clk_freq >> 1;
900 sclk
[all...] |
| H A D | dw_mmc.c | 406 unsigned long sclk; local
416 sclk = host->get_mmc_clk(host, freq);
418 sclk = host->bus_hz;
424 if (sclk == freq)
427 div = DIV_ROUND_UP(sclk, 2 * freq);
|
| H A D | ftsdc010_mci.c | 141 if (rate >= chip->sclk / (2 * (div + 1)))
144 chip->rate = chip->sclk / (2 * (div + 1));
413 chip->sclk = priv->minmax[1];
|
| /u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 369 unsigned long sclk = 0; local
439 sclk = exynos5_get_pll_clk(MPLL);
442 sclk = exynos5_get_pll_clk(EPLL);
445 sclk = exynos5_get_pll_clk(VPLL);
462 return (sclk / (div + 1)) / (sub_div + 1);
468 unsigned long sclk = 0; local
530 sclk = exynos542x_get_pll_clk(MPLL);
533 sclk = exynos542x_get_pll_clk(SPLL);
536 sclk = exynos542x_get_pll_clk(EPLL);
539 sclk
641 unsigned long pclk, sclk; local
682 unsigned long pclk, sclk; local
698 unsigned long uclk, sclk; local
745 unsigned long uclk, sclk; local
789 unsigned long uclk, sclk; local
918 unsigned long pclk, sclk; local
960 unsigned long pclk, sclk; local
1001 unsigned long pclk, sclk; local
1035 unsigned long sclk; local
1579 unsigned long sclk, aclk_100; local
[all...] |
| /u-boot/board/freescale/common/ |
| H A D | ngpixis.c | 141 printf("sclk=%02x%02x%02x\n",
142 PIXIS_READ(sclk[0]), PIXIS_READ(sclk[1]), PIXIS_READ(sclk[2]));
169 PIXIS_WRITE(sclk[0], sclk0);
170 PIXIS_WRITE(sclk[1], sclk1);
171 PIXIS_WRITE(sclk[2], sclk2);
|
| H A D | ics307_clk.c | 136 in_8(&fpga_reg->sclk[0]),
137 in_8(&fpga_reg->sclk[1]),
138 in_8(&fpga_reg->sclk[2]));
|
| H A D | ngpixis.h | 38 u8 sclk[3]; member in struct:ngpixis
|
| H A D | qixis.c | 215 printf("sclk = %02x%02x%02x\n", QIXIS_READ(sclk[0]),
216 QIXIS_READ(sclk[1]), QIXIS_READ(sclk[2]));
|
| H A D | qixis.h | 52 u8 sclk[3]; /* Clock Configuration Registers,0x34 */ member in struct:qixis
|
| /u-boot/drivers/reset/ |
| H A D | reset-at91.c | 91 struct clk sclk; local
99 ret = clk_get_by_index(dev, 0, &sclk);
103 return clk_prepare_enable(&sclk);
|
| /u-boot/drivers/spi/ |
| H A D | soft_spi.c | 28 struct gpio_desc sclk; member in struct:soft_spi_plat
47 dm_gpio_set_value(&plat->sclk, bit);
70 dm_gpio_set_value(&plat->sclk, cidle); /* to idle */
256 ret = gpio_request_by_name(dev, "gpio-sck", 0, &plat->sclk,
259 ret = gpio_request_by_name(dev, "sck-gpios", 0, &plat->sclk,
|
| /u-boot/drivers/i2c/ |
| H A D | octeon_i2c.c | 610 static void twsi_calc_div(struct udevice *bus, ulong sclk, unsigned int speed, argument
619 tclk = sclk / (2 * (thp + 1));
622 sclk = 100000000; /* 100 Mhz */
623 tclk = sclk / (thp + 2);
625 debug("%s( io_clock %lu tclk %u)\n", __func__, sclk, tclk);
|
| /u-boot/drivers/mtd/nand/raw/ |
| H A D | octeontx_nand.c | 563 unsigned long sclk)
569 s_wh = timing_to_cycle(timings->tWH_min, sclk);
570 s_cls = timing_to_cycle(timings->tCLS_min, sclk);
571 s_clh = timing_to_cycle(timings->tCLH_min, sclk);
572 s_rp = timing_to_cycle(timings->tRP_min, sclk);
573 s_wb = timing_to_cycle(timings->tWB_max, sclk);
574 s_wc = timing_to_cycle(timings->tWC_min, sclk);
596 unsigned long sclk = octeontx_get_io_clock(); local
598 set_timings(NULL, &default_timing_parms, timings, sclk);
606 unsigned long sclk local
560 set_timings(struct octeontx_nand_chip *chip, struct ndf_set_tm_par_cmd *tp, const struct nand_sdr_timings *timings, unsigned long sclk) argument
[all...] |