Searched refs:reg_base (Results 1 - 25 of 55) sorted by relevance

123

/u-boot/arch/arm/mach-uniphier/clk/
H A Dpll.h14 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq,
16 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base);
17 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi);
18 int uniphier_ld20_vpll27_init(unsigned long reg_base);
19 int uniphier_ld20_dspll_init(unsigned long reg_base);
H A Dpll-base-ld20.c32 int uniphier_ld20_sscpll_init(unsigned long reg_base, unsigned int freq, argument
35 void __iomem *base = sc_base + reg_base;
63 int uniphier_ld20_sscpll_ssc_en(unsigned long reg_base) argument
65 void __iomem *base = sc_base + reg_base;
75 int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi) argument
77 void __iomem *base = sc_base + reg_base;
88 int uniphier_ld20_vpll27_init(unsigned long reg_base) argument
90 void __iomem *base = sc_base + reg_base;
108 int uniphier_ld20_dspll_init(unsigned long reg_base) argument
110 void __iomem *base = sc_base + reg_base;
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/u-boot/drivers/ata/
H A Dahci_sunxi.c20 static int sunxi_ahci_phy_init(u8 *reg_base) argument
25 writel(0, reg_base + AHCI_RWCR);
28 setbits_le32(reg_base + AHCI_PHYCS1R, 0x1 << 19);
29 clrsetbits_le32(reg_base + AHCI_PHYCS0R,
32 clrsetbits_le32(reg_base + AHCI_PHYCS1R,
35 setbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 28) | (0x1 << 15));
36 clrbits_le32(reg_base + AHCI_PHYCS1R, (0x1 << 19));
37 clrsetbits_le32(reg_base + AHCI_PHYCS0R, (0x7 << 20), (0x3 << 20));
38 clrsetbits_le32(reg_base + AHCI_PHYCS2R, (0x1f << 5), (0x19 << 5));
41 setbits_le32(reg_base
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/u-boot/drivers/pci/
H A Dpcie_plda_common.h48 * @reg_base: The base address of controller register space
56 void __iomem *reg_base; member in struct:pcie_plda
77 value = readl(plda->reg_base + GEN_SETTINGS);
79 writel(value, plda->reg_base + GEN_SETTINGS);
86 value = readl(plda->reg_base + PCIE_PCI_IDS);
89 writel(value, plda->reg_base + PCIE_PCI_IDS);
96 value = readl(plda->reg_base + PCIE_WINROM);
98 writel(value, plda->reg_base + PCIE_WINROM);
105 value = readl(plda->reg_base + PMSG_SUPPORT_RX);
107 writel(value, plda->reg_base
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H A Dpci_ftpci100.c9 void *reg_base; member in struct:ftpci100_data
26 struct ftpci100_ahbc *regs = priv->reg_base;
41 struct ftpci100_ahbc *regs = priv->reg_base;
71 priv->reg_base = phys_to_virt(io->phys_start);
72 if (!priv->reg_base)
/u-boot/drivers/watchdog/
H A Dmeson_gxbb_wdt.c29 void __iomem *reg_base; member in struct:amlogic_wdt_priv
42 writel(timeout_ms, data->reg_base + GXBB_WDT_TCNT_REG);
51 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) & ~GXBB_WDT_CTRL_EN,
52 data->reg_base + GXBB_WDT_CTRL_REG);
61 writel(readl(data->reg_base + GXBB_WDT_CTRL_REG) | GXBB_WDT_CTRL_EN,
62 data->reg_base + GXBB_WDT_CTRL_REG);
71 writel(0, data->reg_base + GXBB_WDT_RSET_REG);
80 writel(0, data->reg_base + GXBB_WDT_CTRL_SYS_RESET_NOW);
90 data->reg_base = dev_remap_addr(dev);
91 if (!data->reg_base)
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/u-boot/drivers/mmc/
H A Dkona_sdhci.c82 void *reg_base; local
92 reg_base = (void *)CONFIG_SYS_SDIO_BASE0;
93 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO0_MAX_CLK,
97 reg_base = (void *)CONFIG_SYS_SDIO_BASE1;
98 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO1_MAX_CLK,
102 reg_base = (void *)CONFIG_SYS_SDIO_BASE2;
103 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO2_MAX_CLK,
107 reg_base = (void *)CONFIG_SYS_SDIO_BASE3;
108 ret = clk_sdio_enable(reg_base, CONFIG_SYS_SDIO3_MAX_CLK,
122 host->ioaddr = reg_base;
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H A Dowl_mmc.c108 void *reg_base; member in struct:owl_mmc_priv
137 setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_EN_BSEL);
139 writel(data->blocks, priv->reg_base + OWL_REG_SD_BLK_NUM);
140 writel(data->blocksize, priv->reg_base + OWL_REG_SD_BLK_SIZE);
144 writel(total, priv->reg_base + OWL_REG_SD_BUF_SIZE);
146 writel(512, priv->reg_base + OWL_REG_SD_BUF_SIZE);
154 owl_dma_config(priv, (ulong) priv->reg_base +
159 owl_dma_config(priv, buf, (ulong) priv->reg_base +
175 setbits_le32(priv->reg_base + OWL_REG_SD_EN, OWL_SD_ENABLE);
198 mode |= (readl(priv->reg_base
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/u-boot/drivers/net/pfe_eth/
H A Dpfe_mdio.c22 void *reg_base = bus->priv; local
33 writel(reg_data, reg_base + EMAC_MII_DATA_REG);
38 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
48 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
56 void *reg_base = bus->priv; local
81 writel(reg_data, reg_base + EMAC_MII_DATA_REG);
86 while (!(readl(reg_base + EMAC_IEVENT_REG) & EMAC_IEVENT_MII)) {
96 writel(EMAC_IEVENT_MII, reg_base + EMAC_IEVENT_REG);
101 val = (u16)readl(reg_base + EMAC_MII_DATA_REG);
102 debug("%s: %p phy: 0x%x reg:0x%08x val:%#x\n", __func__, reg_base,
111 void *reg_base = bus->priv; local
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/u-boot/drivers/usb/musb-new/
H A Dda8xx.c70 void __iomem *reg_base = musb->ctrl_base; local
83 status = musb_readl(reg_base, DA8XX_USB_INTR_SRC_MASKED_REG);
87 musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
103 int drvvbus = musb_readl(reg_base, DA8XX_USB_STAT_REG);
147 musb_writel(reg_base, DA8XX_USB_END_OF_INTR_REG, 0);
157 void __iomem *reg_base = musb->ctrl_base; local
178 musb_readb(reg_base, DA8XX_USB_CTRL_REG));
199 void __iomem *reg_base = musb->ctrl_base; local
206 musb_writel(reg_base, DA8XX_USB_INTR_MASK_SET_REG, mask);
209 musb_writel(reg_base, DA8XX_USB_INTR_SRC_SET_RE
220 void __iomem *reg_base = musb->ctrl_base; local
230 void *reg_base = dev_read_addr_ptr(dev); local
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H A Dmusb_dsps.c163 void __iomem *reg_base = musb->ctrl_base; local
171 dsps_writel(reg_base, wrp->epintr_set, epmask);
172 dsps_writel(reg_base, wrp->coreintr_set, coremask);
176 dsps_writel(reg_base, wrp->coreintr_set,
193 void __iomem *reg_base = musb->ctrl_base; local
195 dsps_writel(reg_base, wrp->coreintr_clear, wrp->usb_bitmap);
196 dsps_writel(reg_base, wrp->epintr_clear,
199 dsps_writel(reg_base, wrp->eoi, 0);
300 void __iomem *reg_base = musb->ctrl_base; local
316 epintr = dsps_readl(reg_base, wr
427 void __iomem *reg_base = musb->ctrl_base; local
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H A Dam35x.c98 void __iomem *reg_base = musb->ctrl_base; local
105 musb_writel(reg_base, EP_INTR_MASK_SET_REG, epmask);
106 musb_writel(reg_base, CORE_INTR_MASK_SET_REG, AM35X_INTR_USB_MASK);
110 musb_writel(reg_base, CORE_INTR_SRC_SET_REG,
122 void __iomem *reg_base = musb->ctrl_base; local
124 musb_writel(reg_base, CORE_INTR_MASK_CLEAR_REG, AM35X_INTR_USB_MASK);
125 musb_writel(reg_base, EP_INTR_MASK_CLEAR_REG,
128 musb_writel(reg_base, USB_END_OF_INTR_REG, 0);
230 void __iomem *reg_base = musb->ctrl_base; local
255 epintr = musb_readl(reg_base, EP_INTR_SRC_MASKED_RE
385 void __iomem *reg_base = musb->ctrl_base; local
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/u-boot/drivers/pci_endpoint/
H A Dpcie-cadence.h230 void __iomem *reg_base; member in struct:cdns_pcie
238 writeb(value, pcie->reg_base + reg);
243 writew(value, pcie->reg_base + reg);
248 writel(value, pcie->reg_base + reg);
253 return readl(pcie->reg_base + reg);
260 writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
266 writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
272 writel(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg);
279 writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg);
285 writew(value, pcie->reg_base
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/u-boot/drivers/spi/
H A Dcadence_qspi_apb.c46 void cadence_qspi_apb_controller_enable(void *reg_base) argument
49 reg = readl(reg_base + CQSPI_REG_CONFIG);
51 writel(reg, reg_base + CQSPI_REG_CONFIG);
54 void cadence_qspi_apb_controller_disable(void *reg_base) argument
57 reg = readl(reg_base + CQSPI_REG_CONFIG);
59 writel(reg, reg_base + CQSPI_REG_CONFIG);
62 void cadence_qspi_apb_dac_mode_enable(void *reg_base) argument
66 reg = readl(reg_base + CQSPI_REG_CONFIG);
68 writel(reg, reg_base + CQSPI_REG_CONFIG);
153 static unsigned int cadence_qspi_wait_idle(void *reg_base) argument
178 cadence_qspi_apb_readdata_capture(void *reg_base, unsigned int bypass, unsigned int delay) argument
202 cadence_qspi_apb_config_baudrate_div(void *reg_base, unsigned int ref_clk_hz, unsigned int sclk_hz) argument
232 cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode) argument
250 cadence_qspi_apb_chipselect(void *reg_base, unsigned int chip_select, unsigned int decoder_enable) argument
284 cadence_qspi_apb_delay(void *reg_base, unsigned int ref_clk, unsigned int sclk_hz, unsigned int tshsl_ns, unsigned int tsd2d_ns, unsigned int tchsh_ns, unsigned int tslch_ns) argument
352 cadence_qspi_apb_exec_flash_cmd(void *reg_base, unsigned int reg) argument
458 void *reg_base = priv->regbase; local
555 void *reg_base = priv->regbase; local
955 cadence_qspi_apb_enter_xip(void *reg_base, char xip_dummy) argument
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H A Dcadence_qspi.h196 #define CQSPI_GET_RD_SRAM_LEVEL(reg_base) \
197 (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \
200 #define CQSPI_GET_WR_SRAM_LEVEL(reg_base) \
201 (((readl((reg_base) + CQSPI_REG_SDRAMLEVEL)) >> \
273 void cadence_qspi_apb_dac_mode_enable(void *reg_base);
293 void cadence_qspi_apb_chipselect(void *reg_base,
295 void cadence_qspi_apb_set_clk_mode(void *reg_base, uint mode);
296 void cadence_qspi_apb_config_baudrate_div(void *reg_base,
298 void cadence_qspi_apb_delay(void *reg_base,
302 void cadence_qspi_apb_enter_xip(void *reg_base, cha
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H A Datmel_spi.c128 struct at91_spi *reg_base = bus_plat->regs; local
148 writel(csrx, &reg_base->csr[cs]);
155 writel(mode, &reg_base->mr);
157 writel(ATMEL_SPI_CR_SPIEN, &reg_base->cr);
207 struct at91_spi *reg_base = bus_plat->regs; local
249 readl(&reg_base->rdr);
253 status = readl(&reg_base->sr);
263 writel(value, &reg_base->tdr);
268 value = readl(&reg_base->rdr);
281 wait_for_bit_le32(&reg_base
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/u-boot/drivers/mtd/nand/raw/
H A Docteontx_bch.h42 void __iomem *reg_base; member in struct:bch_device
52 void __iomem *reg_base; member in struct:bch_vf
117 writeq(num_words, vf->reg_base + BCH_VQX_DOORBELL(0));
H A Docteontx_bch.c83 writeq(1, bch->reg_base + BCH_CTL);
89 writeq(~0ull, bch->reg_base + BCH_ERR_INT_ENA_W1C);
90 writeq(~0ull, bch->reg_base + BCH_ERR_INT);
96 return readq(bch->reg_base + BCH_BIST_RESULT);
174 bch->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
178 debug("%s: base address: %p\n", __func__, bch->reg_base);
360 vf->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0,
362 debug("%s: reg base: %p\n", __func__, vf->reg_base);
371 ctl.u = readq(vf->reg_base + BCH_VQX_CTL(0));
377 writeq(cbuf.u, vf->reg_base
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/u-boot/drivers/phy/rockchip/
H A Dphy-rockchip-pcie.c65 void *reg_base; member in struct:rockchip_pcie_phy
77 writel(reg, priv->reg_base + priv->data->pcie_conf);
84 writel(reg, priv->reg_base + priv->data->pcie_conf);
91 writel(reg, priv->reg_base + priv->data->pcie_conf);
109 writel(reg, priv->reg_base + priv->data->pcie_conf);
114 writel(reg, priv->reg_base + priv->data->pcie_laneoff);
117 ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
131 ret = readl_poll_sleep_timeout(priv->reg_base + priv->data->pcie_status,
144 writel(reg, priv->reg_base + priv->data->pcie_conf);
147 ret = readl_poll_sleep_timeout(priv->reg_base
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H A Dphy-rockchip-inno-usb2.c47 struct regmap *reg_base; member in struct:rockchip_usb2phy
101 property_enable(priv->reg_base, &port_cfg->phy_sus, false);
115 property_enable(priv->reg_base, &port_cfg->phy_sus, true);
193 if (!property_enabled(priv->reg_base, &phy_cfg->clkout_ctl)) {
194 property_enable(priv->reg_base, &phy_cfg->clkout_ctl, true);
216 property_enable(priv->reg_base, &phy_cfg->clkout_ctl, false);
235 priv->reg_base =
238 priv->reg_base = syscon_get_regmap(dev_get_parent(dev));
239 if (IS_ERR(priv->reg_base))
240 return PTR_ERR(priv->reg_base);
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H A Dphy-rockchip-typec.c343 void __iomem *reg_base; member in struct:rockchip_tcphy
399 writel(0x830, priv->reg_base + PMA_CMN_CTRL1);
405 writel(0x90, priv->reg_base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
406 writel(0x960, priv->reg_base + TX_RCVDET_EN_TMR(i));
407 writel(0x30, priv->reg_base + TX_RCVDET_ST_TMR(i));
410 rdata = readl(priv->reg_base + CMN_DIAG_HSCLK_SEL);
413 writel(rdata, priv->reg_base + CMN_DIAG_HSCLK_SEL);
423 priv->reg_base + usb3_pll_cfg[i].addr);
429 writel(0x7799, priv->reg_base + TX_PSC_A0(lane));
430 writel(0x7798, priv->reg_base
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/u-boot/drivers/net/
H A Dmdio_mux_mmioreg.c82 phys_addr_t reg_base, reg_size; local
86 reg_base = ofnode_get_addr_size_index(dev_ofnode(dev), 0, &reg_size);
87 if (reg_base == FDT_ADDR_T_NONE)
108 priv->phys = reg_base;
112 debug("%s: %llx@%lld / %x\n", __func__, reg_base, reg_size, reg_mask);
/u-boot/drivers/reset/
H A Dreset-npcm.c79 void __iomem *reg_base; local
85 reg_base = dev_remap_addr(dev);
86 if (!reg_base)
116 writel(val, reg_base + reg);
/u-boot/drivers/net/octeontx2/
H A Dcgx.c88 reg_addr = lmac->cgx->reg_base +
97 reg_addr = lmac->cgx->reg_base +
119 reg_addr = lmac->cgx->reg_base +
127 reg_addr = lmac->cgx->reg_base +
221 cgx->cgx_id, cgx->reg_base);
256 cgx->reg_base = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0, 0, 0, PCI_REGION_TYPE,
259 cgx->cgx_id = ((u64)(cgx->reg_base) >> 24) & 0x7;
261 debug("%s CGX BAR %p, id: %d\n", __func__, cgx->reg_base,
275 debug("%s: cgx remove reg_base %p cgx_id %d",
276 __func__, cgx->reg_base, cg
[all...]
H A Dcgx.h62 void __iomem *reg_base; member in struct:cgx
71 writeq(val, cgx->reg_base + CMR_SHIFT(lmac) + offset);
76 return readq(cgx->reg_base + CMR_SHIFT(lmac) + offset);

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