Searched refs:reg (Results 1 - 25 of 1136) sorted by relevance

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/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c59 printf("\n write reg 0x%08x = 0x%08x", addr, val);
71 u32 reg; local
75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) &
77 } while (reg); /* Wait for '0' */
117 u32 reg, freq_par, tmp; local
133 reg = reg_read(REG_DFS_ADDR);
135 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS);
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */
142 reg = reg_read(REG_METAL_MASK_ADDR);
144 reg
773 u32 reg, freq_par, tmp; local
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/u-boot/arch/nios2/include/asm/
H A Dptrace.h11 unsigned reg[32]; member in struct:pt_regs
H A Dnios2.h13 #define CTL_STATUS 0 /* Processor status reg */
14 #define CTL_ESTATUS 1 /* Exception status reg */
15 #define CTL_BSTATUS 2 /* Break status reg */
16 #define CTL_IENABLE 3 /* Interrut enable reg */
17 #define CTL_IPENDING 4 /* Interrut pending reg */
23 #define rdctl(reg) __builtin_rdctl(reg)
24 #define wrctl(reg, val) __builtin_wrctl(reg, val)
27 * Control reg bi
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/u-boot/arch/arm/mach-nexell/include/mach/
H A Dsec_reg.h12 int write_sec_reg_by_id(void __iomem *reg, int val, int id);
13 int read_sec_reg_by_id(void __iomem *reg, int id);
14 int read_sec_reg(void __iomem *reg);
15 int write_sec_reg(void __iomem *reg, int val);
/u-boot/arch/arm/include/asm/arch-armv7/
H A Dgenerictimer.h29 * reg: is used in this macro.
32 .macro timer_wait reg, ticks
33 movw \reg, #(\ticks & 0xffff) variable
34 movt \reg, #(\ticks >> 16) variable
35 mcr p15, 0, \reg, c14, c2, 0 variable
37 mov \reg, #3 variable
38 mcr p15, 0, \reg, c14, c2, 1 variable
40 mrc p15, 0, \reg, c14, c2, 1 variable
41 ands \reg, \reg, # variable
43 mov \\reg, #0 variable
44 mcr p15, 0, \\reg, c14, c2, 1 variable
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/u-boot/arch/arm/mach-tegra/
H A Dcache.c18 u32 reg = 0; local
20 /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
34 asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
35 reg &= ~7;
36 reg |= 2;
37 asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));
/u-boot/arch/mips/mach-octeon/include/mach/
H A Dcvmx-fau.h21 static inline u8 *__cvmx_fau_sw_addr(int reg) argument
25 return (cvmx_fau_regs_ptr + reg);
31 * @param reg FAU atomic register to access. 0 <= reg < 2048.
37 static inline int64_t cvmx_fau_fetch_and_add64(cvmx_fau_reg64_t reg, argument
41 return cvmx_hwfau_fetch_and_add64(reg, value);
43 return __atomic_fetch_add(CASTPTR(int64_t, __cvmx_fau_sw_addr(reg)),
50 * @param reg FAU atomic register to access. 0 <= reg < 2048.
56 static inline int32_t cvmx_fau_fetch_and_add32(cvmx_fau_reg32_t reg, argument
75 cvmx_fau_fetch_and_add16(cvmx_fau_reg16_t reg, int16_t value) argument
93 cvmx_fau_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value) argument
116 cvmx_fau_tagwait_fetch_and_add64(cvmx_fau_reg64_t reg, int64_t value) argument
138 cvmx_fau_tagwait_fetch_and_add32(cvmx_fau_reg32_t reg, int32_t value) argument
159 cvmx_fau_tagwait_fetch_and_add16(cvmx_fau_reg16_t reg, int16_t value) argument
179 cvmx_fau_tagwait_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value) argument
201 cvmx_fau_async_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, int64_t value) argument
226 cvmx_fau_async_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, int32_t value) argument
250 cvmx_fau_async_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, int16_t value) argument
273 cvmx_fau_async_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value) argument
300 cvmx_fau_async_tagwait_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, int64_t value) argument
331 cvmx_fau_async_tagwait_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, int32_t value) argument
360 cvmx_fau_async_tagwait_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, int16_t value) argument
388 cvmx_fau_async_tagwait_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value) argument
410 cvmx_fau_atomic_add64(cvmx_fau_reg64_t reg, int64_t value) argument
428 cvmx_fau_atomic_add32(cvmx_fau_reg32_t reg, int32_t value) argument
447 cvmx_fau_atomic_add16(cvmx_fau_reg16_t reg, int16_t value) argument
465 cvmx_fau_atomic_add8(cvmx_fau_reg8_t reg, int8_t value) argument
484 cvmx_fau_atomic_write64(cvmx_fau_reg64_t reg, int64_t value) argument
501 cvmx_fau_atomic_write32(cvmx_fau_reg32_t reg, int32_t value) argument
519 cvmx_fau_atomic_write16(cvmx_fau_reg16_t reg, int16_t value) argument
536 cvmx_fau_atomic_write8(cvmx_fau_reg8_t reg, int8_t value) argument
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H A Docteon_pci.h39 int octeon_pci_io_readb(unsigned int reg);
40 void octeon_pci_io_writeb(int value, unsigned int reg);
41 int octeon_pci_io_readw(unsigned int reg);
42 void octeon_pci_io_writew(int value, unsigned int reg);
43 int octeon_pci_io_readl(unsigned int reg);
44 void octeon_pci_io_writel(int value, unsigned int reg);
45 int octeon_pci_mem1_readb(unsigned int reg);
46 void octeon_pci_mem1_writeb(int value, unsigned int reg);
47 int octeon_pci_mem1_readw(unsigned int reg);
48 void octeon_pci_mem1_writew(int value, unsigned int reg);
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H A Dcvmx-hwfau.h110 * @param reg FAU atomic register to access. 0 <= reg < 2048.
116 static inline u64 __cvmx_hwfau_store_address(u64 noadd, u64 reg) argument
120 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
131 * @param reg FAU atomic register to access. 0 <= reg < 2048.
140 static inline u64 __cvmx_hwfau_atomic_address(u64 tagwait, u64 reg, s64 value) argument
145 cvmx_build_bits(CVMX_FAU_BITS_REGISTER, reg));
151 * @param reg FAU atomic register to access. 0 <= reg < 204
157 cvmx_hwfau_fetch_and_add64(cvmx_fau_reg64_t reg, s64 value) argument
171 cvmx_hwfau_fetch_and_add32(cvmx_fau_reg32_t reg, s32 value) argument
185 cvmx_hwfau_fetch_and_add16(cvmx_fau_reg16_t reg, s16 value) argument
198 cvmx_hwfau_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value) argument
216 cvmx_hwfau_tagwait_fetch_and_add64(cvmx_fau_reg64_t reg, s64 value) argument
239 cvmx_hwfau_tagwait_fetch_and_add32(cvmx_fau_reg32_t reg, s32 value) argument
262 cvmx_hwfau_tagwait_fetch_and_add16(cvmx_fau_reg16_t reg, s16 value) argument
284 cvmx_hwfau_tagwait_fetch_and_add8(cvmx_fau_reg8_t reg, int8_t value) argument
319 __cvmx_fau_iobdma_data(u64 scraddr, s64 value, u64 tagwait, cvmx_fau_op_size_t size, u64 reg) argument
342 cvmx_hwfau_async_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, s64 value) argument
359 cvmx_hwfau_async_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, s32 value) argument
375 cvmx_hwfau_async_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, s16 value) argument
390 cvmx_hwfau_async_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value) argument
410 cvmx_hwfau_async_tagwait_fetch_and_add64(u64 scraddr, cvmx_fau_reg64_t reg, s64 value) argument
431 cvmx_hwfau_async_tagwait_fetch_and_add32(u64 scraddr, cvmx_fau_reg32_t reg, s32 value) argument
451 cvmx_hwfau_async_tagwait_fetch_and_add16(u64 scraddr, cvmx_fau_reg16_t reg, s16 value) argument
470 cvmx_hwfau_async_tagwait_fetch_and_add8(u64 scraddr, cvmx_fau_reg8_t reg, int8_t value) argument
483 cvmx_hwfau_atomic_add64(cvmx_fau_reg64_t reg, s64 value) argument
495 cvmx_hwfau_atomic_add32(cvmx_fau_reg32_t reg, s32 value) argument
508 cvmx_hwfau_atomic_add16(cvmx_fau_reg16_t reg, s16 value) argument
520 cvmx_hwfau_atomic_add8(cvmx_fau_reg8_t reg, int8_t value) argument
533 cvmx_hwfau_atomic_write64(cvmx_fau_reg64_t reg, s64 value) argument
545 cvmx_hwfau_atomic_write32(cvmx_fau_reg32_t reg, s32 value) argument
558 cvmx_hwfau_atomic_write16(cvmx_fau_reg16_t reg, s16 value) argument
570 cvmx_hwfau_atomic_write8(cvmx_fau_reg8_t reg, int8_t value) argument
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/u-boot/drivers/video/exynos/
H A Dexynos_dp_lowlevel.c24 unsigned int reg; local
26 reg = readl(&dp_regs->video_ctl1);
27 reg &= ~VIDEO_EN_MASK;
31 reg |= VIDEO_EN_MASK;
33 writel(reg, &dp_regs->video_ctl1);
41 unsigned int reg; local
43 reg = readl(&dp_regs->video_ctl4);
44 reg &= ~VIDEO_BIST_MASK;
48 reg |= VIDEO_BIST_MASK;
50 writel(reg,
57 unsigned int reg; local
72 unsigned int reg; local
175 unsigned int reg; local
191 unsigned int reg; local
244 unsigned int reg; local
257 unsigned int reg; local
272 unsigned int reg; local
321 unsigned int reg; local
339 unsigned int reg; local
351 unsigned int reg; local
378 unsigned int reg; local
401 unsigned int reg; local
428 unsigned int reg; local
479 unsigned int reg, ret; local
519 unsigned int reg; local
559 unsigned int reg; local
625 unsigned int reg; local
690 unsigned int reg; local
723 unsigned int reg; local
767 unsigned int reg; local
834 unsigned int reg; local
850 unsigned int reg; local
862 unsigned int reg; local
872 unsigned int reg; local
917 unsigned int reg; local
940 unsigned int reg = 0; local
969 unsigned int reg; local
982 unsigned int reg; local
995 unsigned int reg; local
1011 unsigned int reg; local
1045 unsigned int reg; local
1066 unsigned int reg; local
1153 unsigned int reg; local
1172 unsigned int reg; local
1201 unsigned int reg; local
1215 unsigned int reg; local
1231 unsigned int reg; local
1241 unsigned int reg; local
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/u-boot/include/power/
H A Dab8500.h38 #define AB8500_BANK(bank, reg) (((bank) << 8) | (reg))
39 #define AB8500_M_FSM_RANK(reg) AB8500_BANK(0x0, reg)
40 #define AB8500_SYS_CTRL1_BLOCK(reg) AB8500_BANK(0x1, reg)
41 #define AB8500_SYS_CTRL2_BLOCK(reg) AB8500_BANK(0x2, reg)
42 #define AB8500_REGU_CTRL1(reg) AB8500_BANK(0x3, reg)
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/u-boot/board/freescale/t208xrdb/
H A Dcpld.c12 u8 cpld_read(unsigned int reg) argument
16 return in_8(p + reg);
19 void cpld_write(unsigned int reg, u8 value) argument
23 out_8(p + reg, value);
29 u8 reg = CPLD_READ(flash_csr); local
31 reg = (reg & ~CPLD_BANK_SEL_MASK) | CPLD_LBMAP_ALTBANK;
32 CPLD_WRITE(flash_csr, reg);
39 u8 reg = CPLD_READ(flash_csr); local
41 reg
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/u-boot/include/dm/
H A Dpci.h28 * register data. In this case the first cell of the 'reg' property contains
33 * @reg: reg value from dt-plat.c array (first member). This is not a
38 static inline int pci_ofplat_get_devfn(u32 reg) argument
40 return reg & 0xff00;
/u-boot/include/linux/
H A Dlitex.h42 static inline void litex_write8(void __iomem *reg, u8 val) argument
44 _write_litex_subregister(val, reg);
47 static inline void litex_write16(void __iomem *reg, u16 val) argument
49 _write_litex_subregister(val, reg);
52 static inline void litex_write32(void __iomem *reg, u32 val) argument
54 _write_litex_subregister(val, reg);
57 static inline void litex_write64(void __iomem *reg, u64 val) argument
59 _write_litex_subregister(val >> 32, reg);
60 _write_litex_subregister(val, reg + 4);
63 static inline u8 litex_read8(void __iomem *reg) argument
68 litex_read16(void __iomem *reg) argument
73 litex_read32(void __iomem *reg) argument
78 litex_read64(void __iomem *reg) argument
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/u-boot/arch/x86/include/asm/
H A Dintel_regs.h12 #define MCHBAR_REG(reg) (MCH_BASE_ADDRESS + (reg))
22 #define RCB_REG(reg) (RCB_BASE_ADDRESS + (reg))
/u-boot/include/dm/platform_data/
H A Dserial_mxc.h11 struct mxc_uart *reg; /* address of registers in physical memory */ member in struct:mxc_serial_plat
/u-boot/drivers/clk/ti/
H A Dclk.h21 void clk_ti_latch(struct clk_ti_reg *reg, s8 shift);
22 void clk_ti_writel(u32 val, struct clk_ti_reg *reg);
23 u32 clk_ti_readl(struct clk_ti_reg *reg);
24 int clk_ti_get_reg_addr(struct udevice *dev, int index, struct clk_ti_reg *reg);
/u-boot/include/spmi/
H A Dspmi.h10 * @read: read register 'reg' of slave 'usid' and peripheral 'pid'
11 * @write: write register 'reg' of slave 'usid' and peripheral 'pid'
17 int (*read)(struct udevice *dev, int usid, int pid, int reg);
18 int (*write)(struct udevice *dev, int usid, int pid, int reg,
28 * @reg: Register to read
31 int spmi_reg_read(struct udevice *dev, int usid, int pid, int reg);
39 * @reg: Register to write
43 int spmi_reg_write(struct udevice *dev, int usid, int pid, int reg,
/u-boot/arch/arm/mach-imx/
H A Dmisc.c24 int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned argument
28 if ((readl(&reg->reg) & mask) == mask)
36 int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned argument
40 if ((readl(&reg->reg) & mask) == 0)
48 int mxs_reset_block(struct mxs_register_32 *reg) argument
51 writel(MXS_BLOCK_SFTRST, &reg->reg_clr);
53 if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
57 writel(MXS_BLOCK_CLKGATE, &reg
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/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dpmic_bus.h12 int pmic_bus_read(u8 reg, u8 *data);
13 int pmic_bus_write(u8 reg, u8 data);
14 int pmic_bus_setbits(u8 reg, u8 bits);
15 int pmic_bus_clrbits(u8 reg, u8 bits);
/u-boot/arch/x86/include/asm/arch-quark/
H A Dmsg_port.h42 * @reg: register number within a port
44 void msg_port_setup(int op, int port, int reg);
50 * @reg: register number within a port
54 u32 msg_port_read(u8 port, u32 reg);
60 * @reg: register number within a port
63 void msg_port_write(u8 port, u32 reg, u32 value);
69 * @reg: register number within a port
73 u32 msg_port_alt_read(u8 port, u32 reg);
79 * @reg: register number within a port
82 void msg_port_alt_write(u8 port, u32 reg, u3
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/u-boot/drivers/watchdog/
H A Dorion_wdt.c30 void __iomem *reg; member in struct:orion_wdt_priv
55 priv->reg + priv->wdt_counter_offset);
63 u32 reg; local
68 reg = readl(priv->reg + TIMER_CTRL);
69 reg |= WDT_AXP_FIXED_ENABLE_BIT;
70 writel(reg, priv->reg + TIMER_CTRL);
74 priv->reg + priv->wdt_counter_offset);
77 reg
101 u32 reg; local
120 save_reg_from_ofdata(struct udevice *dev, int index, void __iomem **reg, int *offset) argument
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/u-boot/arch/x86/cpu/quark/
H A Dmsg_port.c11 void msg_port_setup(int op, int port, int reg) argument
15 (((reg) << 8) & 0xff00) | MSG_BYTE_ENABLE));
18 u32 msg_port_read(u8 port, u32 reg) argument
23 reg & 0xffffff00);
24 msg_port_setup(MSG_OP_READ, port, reg);
30 void msg_port_write(u8 port, u32 reg, u32 value) argument
34 reg & 0xffffff00);
35 msg_port_setup(MSG_OP_WRITE, port, reg);
38 u32 msg_port_alt_read(u8 port, u32 reg) argument
43 reg
50 msg_port_alt_write(u8 port, u32 reg, u32 value) argument
58 msg_port_io_read(u8 port, u32 reg) argument
70 msg_port_io_write(u8 port, u32 reg, u32 value) argument
[all...]
/u-boot/arch/arm/mach-tegra/tegra20/
H A Dwarmboot_avp.c34 u32 reg; local
41 "adr %0, wb_start;" /* reg: wb_start address */
42 : "=r"(reg) /* output */
46 if (reg != NV_WB_RUN_ADDRESS)
55 reg = readl(&clkrst->crc_rst_dev[TEGRA_DEV_U]);
56 reg |= SWR_CSITE_RST;
57 writel(reg, &clkrst->crc_rst_dev[TEGRA_DEV_U]);
68 reg = PWRGATE_TOGGLE_PARTID_CPU | PWRGATE_TOGGLE_START;
69 writel(reg, &pmc->pmc_pwrgate_toggle);
75 reg
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/u-boot/arch/arm/mach-socfpga/
H A Dclock_manager_gen5.c347 u32 reg, clock; local
350 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_MAINPLL_VCO);
352 clock /= ((reg & CLKMGR_MAINPLLGRP_VCO_DENOM_MASK) >>
354 clock *= ((reg & CLKMGR_MAINPLLGRP_VCO_NUMER_MASK) >>
362 u32 reg, clock = 0; local
365 reg = readl(socfpga_get_clkmgr_addr() + CLKMGR_GEN5_PERPLL_VCO);
366 reg = (reg & CLKMGR_PERPLLGRP_VCO_SSRC_MASK) >>
368 if (reg == CLKMGR_VCO_SSRC_EOSC1)
370 else if (reg
387 u32 reg, clock; local
401 u32 reg, clock = 0; local
432 u32 reg, clock = 0; local
469 u32 reg, clock = 0; local
501 u32 reg, clock = 0; local
531 u32 reg, clock = 0; local
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