| /u-boot/arch/arm/mach-davinci/include/mach/ |
| H A D | dm365_lowlevel.h | 15 int dm365_pll1_init(unsigned long pllmult, unsigned long prediv);
16 int dm365_pll2_init(unsigned long pllm, unsigned long prediv);
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| H A D | pll_defs.h | 19 unsigned int prediv; /* 0x114 */ member in struct:dv_pll_regs
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| H A D | hardware.h | 205 dv_reg prediv; member in struct:davinci_pllc_regs
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| /u-boot/drivers/clk/starfive/ |
| H A D | clk-jh7110-pll.c | 47 u32 prediv; member in struct:starfive_pllx_rate
54 u32 prediv; member in struct:starfive_pllx_offset
99 .prediv = (_pd), \
134 .prediv = 0x24,
151 .prediv = 0x2c,
168 .prediv = 0x34,
230 PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv);
249 u32 prediv, fbdiv, postdiv1; local
256 prediv
[all...] |
| /u-boot/drivers/clk/imx/ |
| H A D | clk-composite-8m.c | 60 int *prediv, int *postdiv)
66 *prediv = 1;
74 *prediv = div1;
58 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) argument
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| /u-boot/drivers/video/rockchip/ |
| H A D | rk_mipi.c | 192 * Mipi dphy config function. Calculate the suitable prediv, feedback div,
202 u64 prediv = 1; local
257 * it's equal to ddr_clk= pixclk * 6. 40MHz >= refclk / prediv >= 5MHz
275 prediv = i;
279 fbdiv = ddr_clk * prediv / refclk;
280 ddr_clk = refclk * fbdiv / prediv;
284 __func__, refclk, prediv, fbdiv, ddr_clk);
286 /* config prediv and feedback reg */
287 test_data[0] = prediv - 1;
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| /u-boot/arch/arm/mach-keystone/ |
| H A D | clock.c | 281 unsigned long mult = 1, prediv = 1, output_div = 2; local
290 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
299 ret = ret / prediv / output_div * mult;
331 prediv = (tmp & CFG_PLLCTL0_PLLD_MASK) + 1;
336 ret = ((ret / prediv) * mult) / output_div;
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | clock_defs.h | 23 u32 prediv; /* 14 */ member in struct:pllctl_regs
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| /u-boot/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-hdmi.c | 144 u8 prediv; member in struct:pre_pll_config
159 u8 prediv; member in struct:post_pll_config
557 inno_write(inno, 0xa1, RK3328_PRE_PLL_PRE_DIV(cfg->prediv));
622 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
630 RK3328_POST_PLL_PRE_DIV(cfg->prediv));
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| H A D | phy-rockchip-inno-dsidphy.c | 223 u8 prediv; member in struct:inno_dsidphy::__anon86
330 /* 5Mhz < Fref / prediv < 40MHz */
370 inno->pll.prediv = best_prediv;
397 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
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| /u-boot/arch/arm/mach-davinci/ |
| H A D | da850_lowlevel.c | 83 /* program the prediv */
86 ®->prediv);
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| /u-boot/drivers/clk/ |
| H A D | clk_versaclock.c | 310 unsigned int prediv, div; local
314 dm_i2c_read(vc5->i2c, VC5_VCO_CTRL_AND_PREDIV, (uchar *)&prediv, 1);
317 if (prediv & VC5_VCO_CTRL_AND_PREDIV_BYPASS_PREDIV)
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| /u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 543 u32 fbdiv, prediv, postdiv, postdiv_en; local
551 prediv = 1;
572 PHY_PREDIV_MASK << PHY_PREDIV_SHIFT, prediv); local
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