| /u-boot/drivers/clk/microchip/ |
| H A D | mpfs_clk_msspll.c | 63 u32 mult, ref_div, postdiv; local
70 postdiv = readl(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT;
71 postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH);
73 temp = msspll_hw->prate / (ref_div * MSSPLL_FIXED_DIV * postdiv);
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| /u-boot/arch/arm/mach-davinci/include/mach/ |
| H A D | pll_defs.h | 24 unsigned int postdiv; /* 0x128 */ member in struct:dv_pll_regs
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| H A D | hardware.h | 210 dv_reg postdiv; member in struct:davinci_pllc_regs
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| /u-boot/drivers/clk/mediatek/ |
| H A D | clk-mtk.c | 90 u32 fin, u32 pcw, int postdiv)
112 return ((unsigned long)vco + postdiv - 1) / postdiv;
121 static void mtk_pll_set_rate_regs(struct clk *clk, u32 pcw, int postdiv) argument
127 /* set postdiv */
130 val |= (ffs(postdiv) - 1) << pll->pd_shift;
132 /* postdiv and pcw need to set at the same time if on same register */
159 * @postdiv: The post divider (output)
162 static void mtk_pll_calc_values(struct clk *clk, u32 *pcw, u32 *postdiv, argument
176 *postdiv
89 __mtk_pll_recalc_rate(const struct mtk_pll_data *pll, u32 fin, u32 pcw, int postdiv) argument
192 u32 postdiv; local
204 u32 postdiv; local
[all...] |
| /u-boot/arch/mips/mach-ath79/qca956x/ |
| H A D | clk.c | 313 u32 out_div, ref_div, postdiv, nint, hfrac, lfrac, clk_ctrl; local
369 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
375 cpu_rate = ddr_pll / (postdiv + 1);
377 cpu_rate = cpu_pll / (postdiv + 1);
379 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
385 ddr_rate = cpu_pll / (postdiv + 1);
387 ddr_rate = ddr_pll / (postdiv + 1);
389 postdiv = (clk_ctrl >> QCA956X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
395 ahb_rate = ddr_pll / (postdiv + 1);
397 ahb_rate = cpu_pll / (postdiv
[all...] |
| /u-boot/drivers/clk/imx/ |
| H A D | clk-composite-8m.c | 60 int *prediv, int *postdiv)
67 *postdiv = 1;
75 *postdiv = div2;
58 imx8m_clk_composite_compute_dividers(unsigned long rate, unsigned long parent_rate, int *prediv, int *postdiv) argument
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| /u-boot/include/ |
| H A D | k3-clk.h | 94 struct postdiv_data postdiv; member in union:clk_data::__anon135
157 .clk.postdiv = {.name = _name, .parent = _parent, .width = _width, .flags = _flags } \
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| /u-boot/drivers/clk/rockchip/ |
| H A D | clk_pll.c | 551 u64 rate, postdiv; local
584 postdiv = p;
585 postdiv *= 65536;
586 do_div(frac_rate64, postdiv);
592 postdiv = p;
593 postdiv *= 65536;
594 do_div(frac_rate64, postdiv);
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| /u-boot/arch/arm/mach-davinci/ |
| H A D | da850_lowlevel.c | 92 /* program the postdiv */
95 ®->postdiv);
98 ®->postdiv);
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| /u-boot/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-hdmi.c | 161 u8 postdiv; member in struct:post_pll_config
620 if (cfg->postdiv == 1) {
626 v = (cfg->postdiv / 2) - 1;
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| /u-boot/drivers/ram/rockchip/ |
| H A D | sdram_rv1126.c | 543 u32 fbdiv, prediv, postdiv, postdiv_en; local
554 postdiv = 2;
558 postdiv = 1;
562 postdiv = 0;
575 postdiv << PHY_POSTDIV_SHIFT);
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