#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
1bcc7a4d |
|
12-Mar-2024 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62px: introduce clock and device files for wkup spl Include the clock and lpsc tree files needed for the wkup spl to initialize the proper PLLs and power domains to boot the SoC. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
95209994 |
|
23-Feb-2024 |
Apurva Nandan <a-nandan@ti.com> |
arm: mach-k3: j784s4: Add clk and power support Add clk and device data which can be used by respective drivers to configure clocks and PSC. Signed-off-by: Hari Nagalla <hnagalla@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Reviewed-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Nishanth Menon <nm@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Roger Quadros <rogerq@kernel.org> Tested-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> # AM69-SK
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
a94a4071 |
|
01-Nov-2023 |
Nishanth Menon <nm@ti.com> |
tree-wide: Replace http:// link with https:// link for ti.com Replace instances of http://www.ti.com with https://www.ti.com Signed-off-by: Nishanth Menon <nm@ti.com>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b6cbcd61 |
|
03-Nov-2022 |
Bryan Brattlof <bb@ti.com> |
arm: mach-k3: am62a: introduce auto-generated SoC data Introduce the auto-generated clock tree and power domain data needed to attach the am62a into the power-domain and clock frameworks of uboot Signed-off-by: Bryan Brattlof <bb@ti.com>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
4b8903a9 |
|
25-May-2022 |
Suman Anna <s-anna@ti.com> |
arm: mach-k3: am62: Introduce autogenerated SoC data Introduce autogenerated SoC data support clk and device data for the AM62. Hook it upto to power-domain and clk frameworks of U-Boot. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
55bdc200 |
|
25-Jan-2022 |
David Huang <d-huang@ti.com> |
clk: clk-k3: Add support for J721S2 SoC Add support for J721S2 SoC. Signed-off-by: David Huang <d-huang@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
cfd50dfb |
|
07-Sep-2021 |
Suman Anna <s-anna@ti.com> |
clk: ti: k3: Update driver to account for divider flags The K3 SoCs have some PLL output clocks (POSTDIV clocks) which in turn serve as inputs to other HSDIV output clocks. These clocks use the actual value to compute the divider clock rate, and need to be registered with the CLK_DIVIDER_ONE_BASED flags. The current k3-clk driver and data lacks the infrastructure to pass in divider flags. Update the driver and data to account for these divider flags. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
0aa2930c |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
|
#
b4a72a9f |
|
11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
b4a72a9f |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC clocks Add driver to support TI K3 generation SoC clocks. This driver registers the clocks provided via platform data, and adds support for controlling the clocks via DT handles. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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#
0aa2930c |
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11-Jun-2021 |
Tero Kristo <t-kristo@ti.com> |
clk: add support for TI K3 SoC PLL Add support for TI K3 SoC PLLs. This clock type supports enabling/disabling/setting and querying the clock rate for the PLL. The euclidean library routine is used to calculate divider/multiplier rates for the PLLs. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Tero Kristo <kristo@kernel.org>
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