/u-boot/include/ |
H A D | pci_tegra.h | 8 int tegra_pcie_port_index_of_port(struct tegra_pcie_port *port); 10 void tegra_pcie_port_reset(struct tegra_pcie_port *port);
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/u-boot/dts/upstream/include/dt-bindings/memory/ |
H A D | mtk-memory-port.h | 11 #define MTK_M4U_ID(larb, port) (((larb) << 5) | (port)) 15 #define MTK_IFAIOMMU_PERI_ID(port) MTK_M4U_ID(0, port)
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/u-boot/arch/mips/mach-octeon/include/ |
H A D | mangle-port.h | 21 # define __swizzle_addr_b(port) (port) 22 # define __swizzle_addr_w(port) (port) 23 # define __swizzle_addr_l(port) (port) 24 # define __swizzle_addr_q(port) (port) 36 # define __swizzle_addr_b(port) \ 37 (__should_swizzle_addr(port) [all...] |
/u-boot/board/intel/galileo/ |
H A D | galileo.c | 23 u32 base, port, val; local 30 port = base + 0x20; 31 val = inl(port); 33 outl(val, port); 36 port = base + 0x24; 37 val = inl(port); 39 outl(val, port); 42 port = base + 0x28; 43 val = inl(port); 45 outl(val, port); 50 u32 base, port, val; local [all...] |
/u-boot/drivers/misc/ |
H A D | smsc_sio1007.c | 11 static inline u8 sio1007_read(int port, int reg) argument 13 outb(reg, port); 15 return inb(port + 1); 18 static inline void sio1007_write(int port, int reg, int val) argument 20 outb(reg, port); 21 outb(val, port + 1); 24 static inline void sio1007_clrsetbits(int port, int reg, u8 clr, u8 set) argument 26 sio1007_write(port, reg, (sio1007_read(port, reg) & ~clr) | set); 29 void sio1007_enable_serial(int port, in argument 52 sio1007_enable_runtime(int port, int iobase) argument 67 sio1007_gpio_config(int port, int gpio, int dir, int pol, int type) argument 90 sio1007_gpio_get_value(int port, int gpio) argument 109 sio1007_gpio_set_value(int port, int gpio, int val) argument [all...] |
/u-boot/arch/mips/mach-octeon/include/mach/ |
H A D | cvmx-agl.h | 12 * @param port to enable 16 int cvmx_agl_enable(int port); 18 cvmx_helper_link_info_t cvmx_agl_link_get(int port); 23 * @param port interface port to set the link. 28 int cvmx_agl_link_set(int port, cvmx_helper_link_info_t link_info); 32 * AGL (RGMII) port(s).
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H A D | cvmx-pko-internal-ports-range.h | 10 * Allocated a block of internal ports for the specified interface/port 13 * @param port the index of the port within in the interface for which the internal ports 20 int cvmx_pko_internal_ports_alloc(int interface, int port, u64 count); 23 * Free the internal ports associated with the specified interface/port 26 * @param port the index of the port within in the interface for which the internal ports 32 int cvmx_pko_internal_ports_free(int interface, int port);
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/u-boot/include/xen/ |
H A D | events.h | 24 int do_event(evtchn_port_t port, struct pt_regs *regs); 25 void unbind_evtchn(evtchn_port_t port); 29 void *data, evtchn_port_t *port); 32 static inline int notify_remote_via_evtchn(evtchn_port_t port) argument 36 op.port = port;
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/u-boot/drivers/xen/ |
H A D | events.c | 38 void (*handler)(evtchn_port_t port, struct pt_regs *regs, void *data); 44 void default_handler(evtchn_port_t port, struct pt_regs *regs, void *data); 62 printf("port %d still bound!\n", i); 70 int do_event(evtchn_port_t port, struct pt_regs *regs) argument 74 clear_evtchn(port); 76 if (port >= NR_EVS) { 77 printk("WARN: do_event(): Port number too large: %d\n", port); 81 action = &ev_actions[port]; 85 action->handler(port, regs, action->data); 90 evtchn_port_t bind_evtchn(evtchn_port_t port, argument 109 unbind_evtchn(evtchn_port_t port) argument 130 default_handler(evtchn_port_t port, struct pt_regs *regs, void *ignore) argument 144 evtchn_alloc_unbound(domid_t pal, void (*handler)(evtchn_port_t, struct pt_regs *, void *), void *data, evtchn_port_t *port) argument [all...] |
/u-boot/include/dm/platform_data/ |
H A D | serial_coldfire.h | 10 * struct coldfire_serial_plat - information about a coldfire port 12 * @base: Uart port base register address 13 * @port: Uart port index, for cpu with pinmux for uart / gpio 14 * baudrtatre: Uart port baudrate 18 int port; member in struct:coldfire_serial_plat
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/u-boot/drivers/net/fm/ |
H A D | p5020.c | 21 static int is_device_disabled(enum fm_port port) argument 26 return port_to_devdisr[port] & devdisr2; 29 void fman_disable_port(enum fm_port port) argument 34 if (port == FM1_DTSEC1) 37 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 40 void fman_enable_port(enum fm_port port) argument 44 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 47 phy_interface_t fman_port_enet_if(enum fm_port port) argument 52 if (is_device_disabled(port)) 55 if ((port [all...] |
H A D | p5040.c | 27 static int is_device_disabled(enum fm_port port) argument 32 return port_to_devdisr[port] & devdisr2; 35 void fman_disable_port(enum fm_port port) argument 40 if (port == FM1_DTSEC1) 43 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 46 void fman_enable_port(enum fm_port port) argument 50 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 53 phy_interface_t fman_port_enet_if(enum fm_port port) argument 58 if (is_device_disabled(port)) 61 if ((port [all...] |
H A D | p4080.c | 25 static int is_device_disabled(enum fm_port port) argument 30 return port_to_devdisr[port] & devdisr2; 33 void fman_disable_port(enum fm_port port) argument 38 if (port == FM1_DTSEC1) 41 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 44 void fman_enable_port(enum fm_port port) argument 48 clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51 phy_interface_t fman_port_enet_if(enum fm_port port) argument 56 if (is_device_disabled(port)) 59 if ((port [all...] |
H A D | ls1046.c | 36 static int is_device_disabled(enum fm_port port) argument 41 return port_to_devdisr[port] & devdisr2; 44 void fman_disable_port(enum fm_port port) argument 48 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 51 phy_interface_t fman_port_enet_if(enum fm_port port) argument 56 if (is_device_disabled(port)) 59 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) 62 if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) 65 if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10))) 68 if ((port [all...] |
H A D | t1024.c | 21 static int is_device_disabled(enum fm_port port) argument 26 return port_to_devdisr[port] & devdisr2; 29 void fman_disable_port(enum fm_port port) argument 33 setbits_be32(&gur->devdisr2, port_to_devdisr[port]); 36 phy_interface_t fman_port_enet_if(enum fm_port port) argument 41 if (is_device_disabled(port)) 44 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1))) 47 if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == 52 if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == 58 switch (port) { [all...] |
/u-boot/arch/x86/include/asm/arch-quark/ |
H A D | msg_port.h | 38 * msg_port_setup - set up the message port control register 41 * @port: port number on the message bus 42 * @reg: register number within a port 44 void msg_port_setup(int op, int port, int reg); 47 * msg_port_read - read a message port register using normal opcode 49 * @port: port number on the message bus 50 * @reg: register number within a port 52 * @return: message port registe [all...] |
/u-boot/arch/powerpc/cpu/mpc8xxx/ |
H A D | srio.c | 56 * Description: During port initialization, the SRIO port performs 61 * the configured port width. 62 * An SRIO port configured as a 4x port may see one of these scenarios: 68 * An SRIO port configured as a 1x port may fail to complete port 70 * Impact: SRIO port may downtrain to 1x, or may fail to complete 71 * link initialization. Once a port complete 74 srio_erratum_a004034(u8 port) argument 292 srio_boot_master(int port) argument 344 srio_boot_master_release_slave(int port) argument [all...] |
/u-boot/drivers/serial/ |
H A D | serial_sh.c | 26 static int scif_rxfill(struct uart_port *port) argument 28 return sci_in(port, SCRFDR) & 0xff; 31 static int scif_rxfill(struct uart_port *port) argument 33 if ((port->mapbase == 0xffe00000) || 34 (port->mapbase == 0xffe08000)) { 36 return sci_in(port, SCRFDR) & 0xff; 39 return sci_in(port, SCFDR) & SCIF2_RFDC_MASK; 43 static int scif_rxfill(struct uart_port *port) argument 45 return sci_in(port, SCFDR) & SCIF_RFDC_MASK; 49 static void sh_serial_init_generic(struct uart_port *port) argument 69 sh_serial_setbrg_generic(struct uart_port *port, int clk, int baudrate) argument 81 handle_error(struct uart_port *port) argument 101 serial_raw_putc(struct uart_port *port, const char c) argument 113 serial_rx_fifo_level(struct uart_port *port) argument 118 sh_serial_tstc_generic(struct uart_port *port) argument 128 serial_getc_check(struct uart_port *port) argument 144 sh_serial_getc_generic(struct uart_port *port) argument 298 sh_serial_init_nodm(struct uart_port *port) argument 304 sh_serial_putc_nondm(struct uart_port *port, const char c) argument 354 struct uart_port *port = &sh_sci; local 373 struct uart_port *port = &sh_sci; local 380 struct uart_port *port = &sh_sci; local [all...] |
/u-boot/arch/arm/include/asm/arch-imx8/ |
H A D | gpio.h | 19 #define IMX_GPIO_NR(port, index) (((port) * 32) + ((index) & 31))
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/u-boot/arch/arm/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/arch/microblaze/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/arch/mips/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/arch/nios2/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/arch/xtensa/dts/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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/u-boot/include/dt-bindings/pinctrl/ |
H A D | rzg2l-pinctrl.h | 20 /* Convert a port and pin label to its global pin index */ 21 #define RZG2L_GPIO(port, pin) ((port) * RZG2L_PINS_PER_PORT + (pin))
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