1284345Ssjg// SPDX-License-Identifier: GPL-2.0+
2284345Ssjg/*
3284345Ssjg * Copyright 2011 Freescale Semiconductor, Inc.
4284345Ssjg */
5284345Ssjg#include <common.h>
6284345Ssjg#include <phy.h>
7284345Ssjg#include <fm_eth.h>
8284345Ssjg#include <asm/io.h>
9284345Ssjg#include <asm/immap_85xx.h>
10284345Ssjg#include <asm/fsl_serdes.h>
11284345Ssjg
12284345Ssjgstatic u32 port_to_devdisr[] = {
13284345Ssjg	[FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
14284345Ssjg	[FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
15284345Ssjg	[FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
16284345Ssjg	[FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
17284345Ssjg	[FM1_DTSEC5] = FSL_CORENET_DEVDISR2_DTSEC1_5,
18284345Ssjg	[FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1,
19284345Ssjg};
20284345Ssjg
21static int is_device_disabled(enum fm_port port)
22{
23	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
24	u32 devdisr2 = in_be32(&gur->devdisr2);
25
26	return port_to_devdisr[port] & devdisr2;
27}
28
29void fman_disable_port(enum fm_port port)
30{
31	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
32
33	/* don't allow disabling of DTSEC1 as its needed for MDIO */
34	if (port == FM1_DTSEC1)
35		return;
36
37	setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
38}
39
40void fman_enable_port(enum fm_port port)
41{
42	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
43
44	clrbits_be32(&gur->devdisr2, port_to_devdisr[port]);
45}
46
47phy_interface_t fman_port_enet_if(enum fm_port port)
48{
49	ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
50	u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
51
52	if (is_device_disabled(port))
53		return PHY_INTERFACE_MODE_NA;
54
55	if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1)))
56		return PHY_INTERFACE_MODE_XGMII;
57
58	/* handle RGMII first */
59	if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
60		FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_RGMII))
61		return PHY_INTERFACE_MODE_RGMII;
62
63	if ((port == FM1_DTSEC4) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) ==
64		FSL_CORENET_RCWSR11_EC1_FM1_DTSEC4_MII))
65		return PHY_INTERFACE_MODE_MII;
66
67	if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
68		FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_RGMII))
69		return PHY_INTERFACE_MODE_RGMII;
70
71	if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) ==
72		FSL_CORENET_RCWSR11_EC2_FM1_DTSEC5_MII))
73		return PHY_INTERFACE_MODE_MII;
74
75	switch (port) {
76	case FM1_DTSEC1:
77	case FM1_DTSEC2:
78	case FM1_DTSEC3:
79	case FM1_DTSEC4:
80	case FM1_DTSEC5:
81		if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
82			return PHY_INTERFACE_MODE_SGMII;
83		break;
84	default:
85		return PHY_INTERFACE_MODE_NA;
86	}
87
88	return PHY_INTERFACE_MODE_NA;
89}
90