Searched refs:pll_ctrl (Results 1 - 9 of 9) sorted by relevance

/u-boot/drivers/usb/host/
H A Dehci-vf.c65 void __iomem *pll_ctrl; local
69 pll_ctrl = &anadig->pll3_ctrl;
70 clrbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_BYPASS);
71 setbits_le32(pll_ctrl, ANADIG_PLL3_CTRL_ENABLE
76 pll_ctrl = &anadig->pll7_ctrl;
77 clrbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_BYPASS);
78 setbits_le32(pll_ctrl, ANADIG_PLL7_CTRL_ENABLE
/u-boot/arch/m68k/include/asm/
H A Dimmap_5282.h90 typedef struct pll_ctrl { struct
H A Dimmap_5235.h207 typedef struct pll_ctrl { struct
H A Dimmap_520x.h177 typedef struct pll_ctrl { struct
H A Dimmap_5329.h375 typedef struct pll_ctrl { struct
H A Dimmap_5301x.h297 typedef struct pll_ctrl { struct
H A Dimmap_5275.h341 typedef struct pll_ctrl { struct
/u-boot/arch/arm/include/asm/arch-sunxi/
H A Ddisplay.h178 u32 pll_ctrl; /* 0x208 */ member in struct:sunxi_hdmi_reg
/u-boot/drivers/video/sunxi/
H A Dsunxi_display.c131 &hdmi->pll_ctrl);
759 writel(SUNXI_HDMI_PLL_CTRL, &hdmi->pll_ctrl);
763 clrsetbits_le32(&hdmi->pll_ctrl, SUNXI_HDMI_PLL_CTRL_DIV_MASK,

Completed in 82 milliseconds