1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Sunxi platform display controller register and constant defines
4 *
5 * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
6 */
7
8#ifndef _SUNXI_DISPLAY_H
9#define _SUNXI_DISPLAY_H
10
11struct sunxi_de_fe_reg {
12	u32 enable;			/* 0x000 */
13	u32 frame_ctrl;			/* 0x004 */
14	u32 bypass;			/* 0x008 */
15	u32 algorithm_sel;		/* 0x00c */
16	u32 line_int_ctrl;		/* 0x010 */
17	u8 res0[0x0c];			/* 0x014 */
18	u32 ch0_addr;			/* 0x020 */
19	u32 ch1_addr;			/* 0x024 */
20	u32 ch2_addr;			/* 0x028 */
21	u32 field_sequence;		/* 0x02c */
22	u32 ch0_offset;			/* 0x030 */
23	u32 ch1_offset;			/* 0x034 */
24	u32 ch2_offset;			/* 0x038 */
25	u8 res1[0x04];			/* 0x03c */
26	u32 ch0_stride;			/* 0x040 */
27	u32 ch1_stride;			/* 0x044 */
28	u32 ch2_stride;			/* 0x048 */
29	u32 input_fmt;			/* 0x04c */
30	u32 ch3_addr;			/* 0x050 */
31	u32 ch4_addr;			/* 0x054 */
32	u32 ch5_addr;			/* 0x058 */
33	u32 output_fmt;			/* 0x05c */
34	u32 int_enable;			/* 0x060 */
35	u32 int_status;			/* 0x064 */
36	u32 status;			/* 0x068 */
37	u8 res2[0x04];			/* 0x06c */
38	u32 csc_coef00;			/* 0x070 */
39	u32 csc_coef01;			/* 0x074 */
40	u32 csc_coef02;			/* 0x078 */
41	u32 csc_coef03;			/* 0x07c */
42	u32 csc_coef10;			/* 0x080 */
43	u32 csc_coef11;			/* 0x084 */
44	u32 csc_coef12;			/* 0x088 */
45	u32 csc_coef13;			/* 0x08c */
46	u32 csc_coef20;			/* 0x090 */
47	u32 csc_coef21;			/* 0x094 */
48	u32 csc_coef22;			/* 0x098 */
49	u32 csc_coef23;			/* 0x09c */
50	u32 deinterlace_ctrl;		/* 0x0a0 */
51	u32 deinterlace_diag;		/* 0x0a4 */
52	u32 deinterlace_tempdiff;	/* 0x0a8 */
53	u32 deinterlace_sawtooth;	/* 0x0ac */
54	u32 deinterlace_spatcomp;	/* 0x0b0 */
55	u32 deinterlace_burstlen;	/* 0x0b4 */
56	u32 deinterlace_preluma;	/* 0x0b8 */
57	u32 deinterlace_tile_addr;	/* 0x0bc */
58	u32 deinterlace_tile_stride;	/* 0x0c0 */
59	u8 res3[0x0c];			/* 0x0c4 */
60	u32 wb_stride_enable;		/* 0x0d0 */
61	u32 ch3_stride;			/* 0x0d4 */
62	u32 ch4_stride;			/* 0x0d8 */
63	u32 ch5_stride;			/* 0x0dc */
64	u32 fe_3d_ctrl;			/* 0x0e0 */
65	u32 fe_3d_ch0_addr;		/* 0x0e4 */
66	u32 fe_3d_ch1_addr;		/* 0x0e8 */
67	u32 fe_3d_ch2_addr;		/* 0x0ec */
68	u32 fe_3d_ch0_offset;		/* 0x0f0 */
69	u32 fe_3d_ch1_offset;		/* 0x0f4 */
70	u32 fe_3d_ch2_offset;		/* 0x0f8 */
71	u8 res4[0x04];			/* 0x0fc */
72	u32 ch0_insize;			/* 0x100 */
73	u32 ch0_outsize;		/* 0x104 */
74	u32 ch0_horzfact;		/* 0x108 */
75	u32 ch0_vertfact;		/* 0x10c */
76	u32 ch0_horzphase;		/* 0x110 */
77	u32 ch0_vertphase0;		/* 0x114 */
78	u32 ch0_vertphase1;		/* 0x118 */
79	u8 res5[0x04];			/* 0x11c */
80	u32 ch0_horztapoffset0;		/* 0x120 */
81	u32 ch0_horztapoffset1;		/* 0x124 */
82	u32 ch0_verttapoffset;		/* 0x128 */
83	u8 res6[0xd4];			/* 0x12c */
84	u32 ch1_insize;			/* 0x200 */
85	u32 ch1_outsize;		/* 0x204 */
86	u32 ch1_horzfact;		/* 0x208 */
87	u32 ch1_vertfact;		/* 0x20c */
88	u32 ch1_horzphase;		/* 0x210 */
89	u32 ch1_vertphase0;		/* 0x214 */
90	u32 ch1_vertphase1;		/* 0x218 */
91	u8 res7[0x04];			/* 0x21c */
92	u32 ch1_horztapoffset0;		/* 0x220 */
93	u32 ch1_horztapoffset1;		/* 0x224 */
94	u32 ch1_verttapoffset;		/* 0x228 */
95	u8 res8[0x1d4];			/* 0x22c */
96	u32 ch0_horzcoef0[32];		/* 0x400 */
97	u32 ch0_horzcoef1[32];		/* 0x480 */
98	u32 ch0_vertcoef[32];		/* 0x500 */
99	u8 res9[0x80];			/* 0x580 */
100	u32 ch1_horzcoef0[32];		/* 0x600 */
101	u32 ch1_horzcoef1[32];		/* 0x680 */
102	u32 ch1_vertcoef[32];		/* 0x700 */
103	u8 res10[0x280];		/* 0x780 */
104	u32 vpp_enable;			/* 0xa00 */
105	u32 vpp_dcti;			/* 0xa04 */
106	u32 vpp_lp1;			/* 0xa08 */
107	u32 vpp_lp2;			/* 0xa0c */
108	u32 vpp_wle;			/* 0xa10 */
109	u32 vpp_ble;			/* 0xa14 */
110};
111
112struct sunxi_de_be_reg {
113	u8 res0[0x800];			/* 0x000 */
114	u32 mode;			/* 0x800 */
115	u32 backcolor;			/* 0x804 */
116	u32 disp_size;			/* 0x808 */
117	u8 res1[0x4];			/* 0x80c */
118	u32 layer0_size;		/* 0x810 */
119	u32 layer1_size;		/* 0x814 */
120	u32 layer2_size;		/* 0x818 */
121	u32 layer3_size;		/* 0x81c */
122	u32 layer0_pos;			/* 0x820 */
123	u32 layer1_pos;			/* 0x824 */
124	u32 layer2_pos;			/* 0x828 */
125	u32 layer3_pos;			/* 0x82c */
126	u8 res2[0x10];			/* 0x830 */
127	u32 layer0_stride;		/* 0x840 */
128	u32 layer1_stride;		/* 0x844 */
129	u32 layer2_stride;		/* 0x848 */
130	u32 layer3_stride;		/* 0x84c */
131	u32 layer0_addr_low32b;		/* 0x850 */
132	u32 layer1_addr_low32b;		/* 0x854 */
133	u32 layer2_addr_low32b;		/* 0x858 */
134	u32 layer3_addr_low32b;		/* 0x85c */
135	u32 layer0_addr_high4b;		/* 0x860 */
136	u32 layer1_addr_high4b;		/* 0x864 */
137	u32 layer2_addr_high4b;		/* 0x868 */
138	u32 layer3_addr_high4b;		/* 0x86c */
139	u32 reg_ctrl;			/* 0x870 */
140	u8 res3[0xc];			/* 0x874 */
141	u32 color_key_max;		/* 0x880 */
142	u32 color_key_min;		/* 0x884 */
143	u32 color_key_config;		/* 0x888 */
144	u8 res4[0x4];			/* 0x88c */
145	u32 layer0_attr0_ctrl;		/* 0x890 */
146	u32 layer1_attr0_ctrl;		/* 0x894 */
147	u32 layer2_attr0_ctrl;		/* 0x898 */
148	u32 layer3_attr0_ctrl;		/* 0x89c */
149	u32 layer0_attr1_ctrl;		/* 0x8a0 */
150	u32 layer1_attr1_ctrl;		/* 0x8a4 */
151	u32 layer2_attr1_ctrl;		/* 0x8a8 */
152	u32 layer3_attr1_ctrl;		/* 0x8ac */
153	u8 res5[0x110];			/* 0x8b0 */
154	u32 output_color_ctrl;		/* 0x9c0 */
155	u8 res6[0xc];			/* 0x9c4 */
156	u32 output_color_coef[12];	/* 0x9d0 */
157};
158
159struct sunxi_hdmi_reg {
160	u32 version_id;			/* 0x000 */
161	u32 ctrl;			/* 0x004 */
162	u32 irq;			/* 0x008 */
163	u32 hpd;			/* 0x00c */
164	u32 video_ctrl;			/* 0x010 */
165	u32 video_size;			/* 0x014 */
166	u32 video_bp;			/* 0x018 */
167	u32 video_fp;			/* 0x01c */
168	u32 video_spw;			/* 0x020 */
169	u32 video_polarity;		/* 0x024 */
170	u8 res0[0x58];			/* 0x028 */
171	u8 avi_info_frame[0x14];	/* 0x080 */
172	u8 res1[0x4c];			/* 0x094 */
173	u32 qcp_packet0;		/* 0x0e0 */
174	u32 qcp_packet1;		/* 0x0e4 */
175	u8 res2[0x118];			/* 0x0e8 */
176	u32 pad_ctrl0;			/* 0x200 */
177	u32 pad_ctrl1;			/* 0x204 */
178	u32 pll_ctrl;			/* 0x208 */
179	u32 pll_dbg0;			/* 0x20c */
180	u32 pll_dbg1;			/* 0x210 */
181	u32 hpd_cec;			/* 0x214 */
182	u8 res3[0x28];			/* 0x218 */
183	u8 vendor_info_frame[0x14];	/* 0x240 */
184	u8 res4[0x9c];			/* 0x254 */
185	u32 pkt_ctrl0;			/* 0x2f0 */
186	u32 pkt_ctrl1;			/* 0x2f4 */
187	u8 res5[0x8];			/* 0x2f8 */
188	u32 unknown;			/* 0x300 */
189	u8 res6[0xc];			/* 0x304 */
190	u32 audio_sample_count;		/* 0x310 */
191	u8 res7[0xec];			/* 0x314 */
192	u32 audio_tx_fifo;		/* 0x400 */
193	u8 res8[0xfc];			/* 0x404 */
194#ifndef CONFIG_MACH_SUN6I
195	u32 ddc_ctrl;			/* 0x500 */
196	u32 ddc_addr;			/* 0x504 */
197	u32 ddc_int_mask;		/* 0x508 */
198	u32 ddc_int_status;		/* 0x50c */
199	u32 ddc_fifo_ctrl;		/* 0x510 */
200	u32 ddc_fifo_status;		/* 0x514 */
201	u32 ddc_fifo_data;		/* 0x518 */
202	u32 ddc_byte_count;		/* 0x51c */
203	u32 ddc_cmnd;			/* 0x520 */
204	u32 ddc_exreg;			/* 0x524 */
205	u32 ddc_clock;			/* 0x528 */
206	u8 res9[0x14];			/* 0x52c */
207	u32 ddc_line_ctrl;		/* 0x540 */
208#else
209	u32 ddc_ctrl;			/* 0x500 */
210	u32 ddc_exreg;			/* 0x504 */
211	u32 ddc_cmnd;			/* 0x508 */
212	u32 ddc_addr;			/* 0x50c */
213	u32 ddc_int_mask;		/* 0x510 */
214	u32 ddc_int_status;		/* 0x514 */
215	u32 ddc_fifo_ctrl;		/* 0x518 */
216	u32 ddc_fifo_status;		/* 0x51c */
217	u32 ddc_clock;			/* 0x520 */
218	u32 ddc_timeout;		/* 0x524 */
219	u8 res9[0x18];			/* 0x528 */
220	u32 ddc_dbg;			/* 0x540 */
221	u8 res10[0x3c];			/* 0x544 */
222	u32 ddc_fifo_data;		/* 0x580 */
223#endif
224};
225
226/*
227 * DE-FE register constants.
228 */
229#define SUNXI_DE_FE_WIDTH(x)			(((x) - 1) << 0)
230#define SUNXI_DE_FE_HEIGHT(y)			(((y) - 1) << 16)
231#define SUNXI_DE_FE_FACTOR_INT(n)		((n) << 16)
232#define SUNXI_DE_FE_ENABLE_EN			(1 << 0)
233#define SUNXI_DE_FE_FRAME_CTRL_REG_RDY		(1 << 0)
234#define SUNXI_DE_FE_FRAME_CTRL_COEF_RDY		(1 << 1)
235#define SUNXI_DE_FE_FRAME_CTRL_FRM_START	(1 << 16)
236#define SUNXI_DE_FE_BYPASS_CSC_BYPASS		(1 << 1)
237#define SUNXI_DE_FE_INPUT_FMT_ARGB8888		0x00000151
238#define SUNXI_DE_FE_OUTPUT_FMT_ARGB8888		0x00000002
239
240/*
241 * DE-BE register constants.
242 */
243#define SUNXI_DE_BE_WIDTH(x)			(((x) - 1) << 0)
244#define SUNXI_DE_BE_HEIGHT(y)			(((y) - 1) << 16)
245#define SUNXI_DE_BE_MODE_ENABLE			(1 << 0)
246#define SUNXI_DE_BE_MODE_START			(1 << 1)
247#define SUNXI_DE_BE_MODE_DEFLICKER_ENABLE	(1 << 4)
248#define SUNXI_DE_BE_MODE_LAYER0_ENABLE		(1 << 8)
249#define SUNXI_DE_BE_MODE_INTERLACE_ENABLE	(1 << 28)
250#define SUNXI_DE_BE_LAYER_STRIDE(x)		((x) << 5)
251#define SUNXI_DE_BE_REG_CTRL_LOAD_REGS		(1 << 0)
252#define SUNXI_DE_BE_LAYER_ATTR0_SRC_FE0		0x00000002
253#define SUNXI_DE_BE_LAYER_ATTR1_FMT_XRGB8888	(0x09 << 8)
254#define SUNXI_DE_BE_OUTPUT_COLOR_CTRL_ENABLE	1
255
256/*
257 * HDMI register constants.
258 */
259#define SUNXI_HDMI_X(x)				(((x) - 1) << 0)
260#define SUNXI_HDMI_Y(y)				(((y) - 1) << 16)
261#define SUNXI_HDMI_CTRL_ENABLE			(1 << 31)
262#define SUNXI_HDMI_IRQ_STATUS_FIFO_UF		(1 << 0)
263#define SUNXI_HDMI_IRQ_STATUS_FIFO_OF		(1 << 1)
264#define SUNXI_HDMI_IRQ_STATUS_BITS		0x73
265#define SUNXI_HDMI_HPD_DETECT			(1 << 0)
266#define SUNXI_HDMI_VIDEO_CTRL_ENABLE		(1 << 31)
267#define SUNXI_HDMI_VIDEO_CTRL_HDMI		(1 << 30)
268#define SUNXI_HDMI_VIDEO_POL_HOR		(1 << 0)
269#define SUNXI_HDMI_VIDEO_POL_VER		(1 << 1)
270#define SUNXI_HDMI_VIDEO_POL_TX_CLK		(0x3e0 << 16)
271#define SUNXI_HDMI_QCP_PACKET0			3
272#define SUNXI_HDMI_QCP_PACKET1			0
273
274#ifdef CONFIG_MACH_SUN6I
275#define SUNXI_HDMI_PAD_CTRL0_HDP		0x7e80000f
276#define SUNXI_HDMI_PAD_CTRL0_RUN		0x7e8000ff
277#else
278#define SUNXI_HDMI_PAD_CTRL0_HDP		0xfe800000
279#define SUNXI_HDMI_PAD_CTRL0_RUN		0xfe800000
280#endif
281
282#ifdef CONFIG_MACH_SUN4I
283#define SUNXI_HDMI_PAD_CTRL1			0x00d8c820
284#elif defined CONFIG_MACH_SUN6I
285#define SUNXI_HDMI_PAD_CTRL1			0x01ded030
286#else
287#define SUNXI_HDMI_PAD_CTRL1			0x00d8c830
288#endif
289#define SUNXI_HDMI_PAD_CTRL1_HALVE		(1 << 6)
290
291#ifdef CONFIG_MACH_SUN6I
292#define SUNXI_HDMI_PLL_CTRL			0xba48a308
293#define SUNXI_HDMI_PLL_CTRL_DIV(n)		(((n) - 1) << 4)
294#else
295#define SUNXI_HDMI_PLL_CTRL			0xfa4ef708
296#define SUNXI_HDMI_PLL_CTRL_DIV(n)		((n) << 4)
297#endif
298#define SUNXI_HDMI_PLL_CTRL_DIV_MASK		(0xf << 4)
299
300#define SUNXI_HDMI_PLL_DBG0_PLL3		(0 << 21)
301#define SUNXI_HDMI_PLL_DBG0_PLL7		(1 << 21)
302
303#define SUNXI_HDMI_PKT_CTRL0			0x00000f21
304#define SUNXI_HDMI_PKT_CTRL1			0x0000000f
305#define SUNXI_HDMI_UNKNOWN_INPUT_SYNC		0x08000000
306
307#ifdef CONFIG_MACH_SUN6I
308#define SUNXI_HMDI_DDC_CTRL_ENABLE		(1 << 0)
309#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE		(1 << 4)
310#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE		(1 << 6)
311#define SUNXI_HMDI_DDC_CTRL_START		(1 << 27)
312#define SUNXI_HMDI_DDC_CTRL_RESET		(1 << 31)
313#else
314#define SUNXI_HMDI_DDC_CTRL_RESET		(1 << 0)
315/* sun4i / sun5i / sun7i do not have a separate line_ctrl reg */
316#define SUNXI_HMDI_DDC_CTRL_SDA_ENABLE		0
317#define SUNXI_HMDI_DDC_CTRL_SCL_ENABLE		0
318#define SUNXI_HMDI_DDC_CTRL_START		(1 << 30)
319#define SUNXI_HMDI_DDC_CTRL_ENABLE		(1 << 31)
320#endif
321
322#ifdef CONFIG_MACH_SUN6I
323#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR		(0xa0 << 0)
324#else
325#define SUNXI_HMDI_DDC_ADDR_SLAVE_ADDR		(0x50 << 0)
326#endif
327#define SUNXI_HMDI_DDC_ADDR_OFFSET(n)		(((n) & 0xff) << 8)
328#define SUNXI_HMDI_DDC_ADDR_EDDC_ADDR		(0x60 << 16)
329#define SUNXI_HMDI_DDC_ADDR_EDDC_SEGMENT(n)	((n) << 24)
330
331#ifdef CONFIG_MACH_SUN6I
332#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR		(1 << 15)
333#else
334#define SUNXI_HDMI_DDC_FIFO_CTRL_CLEAR		(1 << 31)
335#endif
336
337#define SUNXI_HDMI_DDC_CMND_EXPLICIT_EDDC_READ	6
338#define SUNXI_HDMI_DDC_CMND_IMPLICIT_EDDC_READ	7
339
340#ifdef CONFIG_MACH_SUN6I
341#define SUNXI_HDMI_DDC_CLOCK			0x61
342#else
343/* N = 5,M=1 Fscl= Ftmds/2/10/2^N/(M+1) */
344#define SUNXI_HDMI_DDC_CLOCK			0x0d
345#endif
346
347#define SUNXI_HMDI_DDC_LINE_CTRL_SCL_ENABLE	(1 << 8)
348#define SUNXI_HMDI_DDC_LINE_CTRL_SDA_ENABLE	(1 << 9)
349
350int sunxi_simplefb_setup(void *blob);
351
352#endif /* _SUNXI_DISPLAY_H */
353