Searched refs:pll_clk (Results 1 - 7 of 7) sorted by relevance
| /u-boot/drivers/clk/exynos/ |
| H A D | clk-pll.c | 102 const struct samsung_pll_clock *pll_clk)
113 pll->con_reg = base + pll_clk->con_offset;
114 pll->type = pll_clk->type;
116 clk->flags = pll_clk->flags;
118 switch (pll_clk->type) {
130 ret = clk_register(clk, drv_name, pll_clk->name, pll_clk->parent_name);
147 const struct samsung_pll_clock *pll_clk; local
150 pll_clk = &clk_list[cnt];
151 clk = _samsung_clk_register_pll(base, pll_clk);
101 _samsung_clk_register_pll(void __iomem *base, const struct samsung_pll_clock *pll_clk) argument
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| /u-boot/drivers/clk/imx/ |
| H A D | clk-fracn-gppll.c | 335 const struct imx_fracn_gppll_clk *pll_clk,
347 pll->rate_table = pll_clk->rate_table;
348 pll->rate_count = pll_clk->rate_count;
365 const struct imx_fracn_gppll_clk *pll_clk)
367 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_FRACN);
372 const struct imx_fracn_gppll_clk *pll_clk)
374 return _imx_clk_fracn_gppll(name, parent_name, base, pll_clk, CLK_FRACN_GPPLL_INTEGER);
333 _imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk, u32 pll_flags) argument
364 imx_clk_fracn_gppll(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk) argument
370 imx_clk_fracn_gppll_integer(const char *name, const char *parent_name, void __iomem *base, const struct imx_fracn_gppll_clk *pll_clk) argument
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| H A D | clk-pll14xx.c | 393 const struct imx_pll14xx_clk *pll_clk)
404 switch (pll_clk->type) {
418 pll->type = pll_clk->type;
419 pll->rate_table = pll_clk->rate_table;
420 pll->rate_count = pll_clk->rate_count;
391 imx_clk_pll14xx(const char *name, const char *parent_name, void __iomem *base, const struct imx_pll14xx_clk *pll_clk) argument
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| H A D | clk.h | 69 const struct imx_fracn_gppll_clk *pll_clk);
72 const struct imx_fracn_gppll_clk *pll_clk);
79 const struct imx_pll14xx_clk *pll_clk);
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| /u-boot/drivers/clk/starfive/ |
| H A D | clk-jh7110-pll.c | 325 const struct starfive_pllx_clk *pll_clk)
331 if (!pll_clk || !base || !sysreg)
340 pll->type = pll_clk->type;
341 pll->offset = pll_clk->offset;
342 pll->rate_table = pll_clk->rate_table;
343 pll->rate_count = pll_clk->rate_count;
323 starfive_jh7110_pll(const char *name, const char *parent_name, void __iomem *base, void __iomem *sysreg, const struct starfive_pllx_clk *pll_clk) argument
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| /u-boot/drivers/spi/ |
| H A D | mtk_spim.c | 412 u32 pll_clk, sck_l, sck_h, clk_count, reg; local
421 pll_clk = priv->pll_clk_rate;
424 do_div(pll_clk, sck_l + sck_h + 2);
426 us = CLK_TO_US(pll_clk, clk_count * 8);
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| /u-boot/drivers/phy/rockchip/ |
| H A D | phy-rockchip-inno-dsidphy.c | 220 struct clk *pll_clk; member in struct:inno_dsidphy
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