| /u-boot/test/dm/ |
| H A D | clk_ccf.c | 21 struct clk *clk, *pclk; local
74 ret = clk_get_by_id(SANDBOX_CLK_PLL3_80M, &pclk);
77 ret = clk_set_parent(clk, pclk);
91 pclk = clk_get_parent(clk);
92 ut_asserteq_str("pll3_80m", pclk->dev->name);
93 ut_asserteq(CLK_SET_RATE_PARENT, pclk->flags);
101 ret = clk_get_by_id(SANDBOX_CLK_PLL3_60M, &pclk);
104 ret = clk_set_parent(clk, pclk);
141 ret = clk_get_by_id(SANDBOX_CLK_I2C, &pclk);
144 ret = sandbox_clk_enable_count(pclk);
[all...] |
| /u-boot/drivers/pwm/ |
| H A D | pwm-at91.c | 33 struct clk pclk; member in struct:at91_pwm_priv
175 ret = clk_get_by_index(dev, 0, &priv->pclk);
180 ret = clk_enable(&priv->pclk);
184 priv->clkrate = clk_get_rate(&priv->pclk);
|
| /u-boot/drivers/clk/ |
| H A D | clk-uclass.c | 480 struct clk *pclk; local
489 pclk = dev_get_clk_ptr(pdev);
490 if (!pclk)
493 return pclk;
499 struct clk *pclk; local
505 pclk = clk_get_parent(clk);
506 if (IS_ERR(pclk))
509 ops = clk_dev_ops(pclk->dev);
514 if (!pclk->rate || pclk
[all...] |
| /u-boot/drivers/i2c/ |
| H A D | nx_i2c.c | 125 uint pclk = 0; local
130 pclk = i2c_get_clkrate(bus);
133 /* t_pclk = period time of one pclk [ns] */
134 t_pclk = DIV_ROUND_UP(1000, pclk / 1000000);
168 unsigned long pclk, pres = 16, div; local
174 pclk = i2c_get_clkrate(bus);
177 if ((pclk / pres / (16 + 1)) > speed)
183 while ((pclk / pres / (div + 1)) > speed)
206 bus->speed = pclk / ((div + 1) * pres);
|
| /u-boot/drivers/net/ |
| H A D | dwc_eth_qos_starfive.c | 83 struct clk *pclk, *c; local
118 pclk = clk_get_parent(c);
119 if (pclk) {
120 ret = clk_set_rate(pclk, rate);
|
| H A D | fec_mxc.c | 181 u32 pclk; local
191 pclk = ret;
192 speed = DIV_ROUND_UP(pclk, 5000000);
193 hold = DIV_ROUND_UP(pclk, 100000000) - 1;
|
| H A D | zynq_gem.c | 230 struct clk pclk; member in struct:zynq_gem_priv
329 pclk_hz = clk_get_rate(&priv->pclk);
873 ret = clk_get_by_name(dev, "pclk", &priv->pclk);
875 dev_err(dev, "failed to get pclk clock\n");
|
| /u-boot/drivers/misc/ |
| H A D | sifive-otp.c | 80 u32 pclk; /* Clock input */ member in struct:sifive_otp_regs
137 writel(PCLK_ENABLE_VAL, ®s->pclk);
139 writel(PCLK_DISABLE_VAL, ®s->pclk);
195 writel(PCLK_DISABLE_VAL, ®s->pclk);
|
| /u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 242 unsigned long pclk; local
258 pclk = get_hclk_sys(dom) / (pclk_sys_ratio + 1);
260 return pclk;
|
| /u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 641 unsigned long pclk, sclk; local
674 pclk = sclk / (ratio + 1);
676 return pclk;
682 unsigned long pclk, sclk; local
688 pclk = sclk / (ratio + 1);
690 return pclk;
918 unsigned long pclk, sclk; local
950 pclk = sclk / (ratio + 1);
952 return pclk;
960 unsigned long pclk, scl local
1001 unsigned long pclk, sclk; local
[all...] |
| /u-boot/drivers/net/pfe_eth/ |
| H A D | pfe_mdio.c | 254 u32 pclk = 250000000; local
269 mdio_speed = (DIV_ROUND_UP(pclk, 4000000) << EMAC_MII_SPEED_SHIFT);
|
| /u-boot/drivers/video/stm32/ |
| H A D | stm32_ltdc.c | 533 struct clk pclk; local
544 ret = clk_get_by_index(dev, 0, &pclk);
550 ret = clk_enable(&pclk);
594 rate = clk_set_rate(&pclk, timings.pixelclock.typ);
|
| /u-boot/drivers/spi/ |
| H A D | atmel-quadspi.c | 987 struct clk pclk, qspick, gclk; local
990 ret = clk_get_by_name(dev, "pclk", &pclk);
992 ret = clk_get_by_index(dev, 0, &pclk);
999 ret = clk_enable(&pclk);
1028 aq->bus_clk_rate = clk_get_rate(&pclk);
|
| /u-boot/drivers/clk/starfive/ |
| H A D | clk-jh7110.c | 236 struct clk *pclk; local
448 if (!clk_get_by_id(JH7110_SYSCLK_NOC_BUS_STG_AXI, &pclk))
449 clk_enable(pclk);
|
| /u-boot/drivers/video/tegra124/ |
| H A D | display.c | 31 int pclk = timing->pixelclock.typ; local
37 if (!pclk || !h_total || !v_total)
39 refresh = pclk / h_total;
50 debug("MODE:%dx%d@%d.%03uHz pclk=%d\n",
|
| /u-boot/drivers/video/bridge/ |
| H A D | tc358768.c | 304 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) argument
306 return (u32)div_u64((u64)pclk * priv->pd_lines, priv->dsi_lanes);
433 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) argument
435 return (u32)div_u64((u64)val * NANO, pclk);
536 log_debug("%s: dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", __func__,
|
| /u-boot/drivers/video/rockchip/ |
| H A D | dw_mipi_dsi_rockchip.c | 234 struct clk *pclk; member in struct:dw_rockchip_dsi_priv
852 priv->pclk = devm_clk_get(dev, "pclk");
853 if (IS_ERR(priv->pclk)) {
854 ret = PTR_ERR(priv->pclk);
|