Searched refs:mckr (Results 1 - 10 of 10) sorted by relevance

/u-boot/arch/arm/mach-at91/armv7/
H A Dclock.c59 unsigned freq, mckr; local
86 mckr = readl(&pmc->mckr);
89 if (mckr & (1 << 12))
92 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
96 freq >>= mckr & AT91_PMC_MCKR_PRES_MASK;
98 switch (mckr & AT91_PMC_MCKR_MDIV_MASK) {
126 void at91_mck_init(u32 mckr) argument
131 tmp = readl(&pmc->mckr);
140 tmp |= mckr
160 at91_mck_init_down(u32 mckr) argument
[all...]
/u-boot/arch/arm/mach-at91/include/mach/
H A Dat91_common.h26 void at91_mck_init(u32 mckr);
27 void at91_mck_init_down(u32 mckr);
32 void at91_mck_init(u32 mckr);
H A Dclk.h65 return readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV;
H A Dat91_pmc.h42 u32 mckr; /* 0x30 Master Clock Register */ member in struct:at91_pmc
/u-boot/arch/arm/mach-at91/arm926ejs/
H A Dclock.c116 unsigned freq, mckr; local
156 mckr = readl(&pmc->mckr);
160 gd->arch.plla_rate_hz /= (1 << ((mckr & 1 << 12) >> 12));
162 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
167 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 4));
169 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
174 gd->arch.mck_rate_hz = (mckr & AT91_PMC_MCKR_MDIV_MASK) ?
175 freq / ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 7) : freq;
176 if (mckr
220 at91_mck_init(u32 mckr) argument
[all...]
/u-boot/arch/arm/mach-at91/
H A Dspl_at91.c48 if ((readl(&pmc->mckr) & AT91_PMC_CSS) == AT91_PMC_CSS_SLOW) {
51 tmp = readl(&pmc->mckr);
54 writel(tmp, &pmc->mckr);
60 writel(tmp, &pmc->mckr);
/u-boot/arch/arm/mach-at91/arm920t/
H A Dclock.c108 unsigned freq, mckr; local
148 mckr = readl(&pmc->mckr);
149 gd->arch.mck_rate_hz = at91_css_to_rate(mckr & AT91_PMC_MCKR_CSS_MASK);
152 freq /= (1 << ((mckr & AT91_PMC_MCKR_PRES_MASK) >> 2)); /* prescale */
155 (1 + ((mckr & AT91_PMC_MCKR_MDIV_MASK) >> 8));
/u-boot/drivers/clk/at91/
H A Dclk-master.c85 unsigned int mckr; local
91 pmc_read(master->base, master->layout->offset, &mckr);
92 mckr &= layout->mask;
94 pres = (mckr >> layout->pres_shift) & MASTER_PRES_MASK;
161 unsigned int mckr; local
167 pmc_read(master->base, master->layout->offset, &mckr);
168 mckr &= layout->mask;
169 div = (mckr >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
H A Dcompat.c297 if (readl(&pmc->mckr) & AT91_PMC_MCKR_PLLADIV_2)
320 writel((readl(&pmc->mckr) | AT91_PMC_MCKR_PLLADIV_2),
321 &pmc->mckr);
688 if (readl(&pmc->mckr) & AT91_PMC_MCKR_H32MXDIV)
/u-boot/board/esd/meesc/
H A Dmeesc.c241 writel((readl(&pmc->mckr) & ~AT91_PMC_MDIV) |
242 AT91SAM9_PMC_MDIV_4, &pmc->mckr);

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