Searched refs:l2cache (Results 1 - 5 of 5) sorted by relevance
| /u-boot/arch/powerpc/cpu/mpc85xx/ |
| H A D | spl_minimal.c | 18 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; local
20 out_be32(&l2cache->l2srbar0, CFG_SYS_INIT_L2_ADDR);
23 out_be32(&l2cache->l2errdis,
27 out_be32(&l2cache->l2ctl,
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| H A D | cpu_init_early.c | 91 ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; local
147 out_be32(&l2cache->l2srbar0, SRAM_BASE_ADDR);
149 out_be32(&l2cache->l2errdis,
152 out_be32(&l2cache->l2ctl,
172 clrbits_be32(&l2cache->l2ctl,
175 out_be32(&l2cache->l2srbar0, 0x0);
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| H A D | cpu_init.c | 458 struct ccsr_cluster_l2 __iomem *l2cache; local
478 l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
494 clrsetbits_be32(&l2cache->l2csr1, 0xff, 32 + i * 2 + 1);
496 printf("enable l2 for cluster %d %p\n", i, l2cache);
498 out_be32(&l2cache->l2csr0, L2CSR0_L2FI|L2CSR0_L2LFC);
499 while ((in_be32(&l2cache->l2csr0)
502 out_be32(&l2cache->l2csr0, L2CSR0_L2E|L2CSR0_L2PE|L2CSR0_L2REP_MODE);
518 ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR; local
520 struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2; local
533 cache_ctl = l2cache
[all...] |
| H A D | fdt.c | 223 volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; local
224 volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
299 struct ccsr_cluster_l2 *l2cache = local
301 u32 l2cfg0 = in_be32(&l2cache->l2cfg0);
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| /u-boot/drivers/cache/ |
| H A D | cache-andes-l2.c | 17 struct l2cache { struct
77 struct l2cache *regs;
87 volatile struct l2cache *regs = plat->regs;
98 volatile struct l2cache *regs = plat->regs;
120 struct l2cache *regs;
144 struct l2cache *regs = plat->regs;
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