Searched refs:i2c (Results 1 - 25 of 456) sorted by relevance

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/u-boot/drivers/i2c/
H A Dmeson_i2c.c10 #include <i2c.h>
64 static void meson_i2c_reset_tokens(struct meson_i2c *i2c) argument
66 i2c->tokens[0] = 0;
67 i2c->tokens[1] = 0;
68 i2c->num_tokens = 0;
71 static void meson_i2c_add_token(struct meson_i2c *i2c, int token) argument
73 if (i2c->num_tokens < 8)
74 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
76 i2c
85 meson_i2c_get_data(struct meson_i2c *i2c, u8 *buf, int len) argument
106 meson_i2c_put_data(struct meson_i2c *i2c, u8 *buf, int len) argument
128 meson_i2c_prepare_xfer(struct meson_i2c *i2c) argument
155 meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg) argument
167 meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg, int last) argument
219 struct meson_i2c *i2c = dev_get_priv(bus); local
233 struct meson_i2c *i2c = dev_get_priv(bus); local
262 struct meson_i2c *i2c = dev_get_priv(bus); local
[all...]
H A Docores_i2c.c3 * ocores-i2c.c: I2C bus driver for OpenCores I2C controller
4 * (https://opencores.org/projects/i2c)
21 #include <i2c.h>
75 void (*setreg)(struct ocores_i2c_bus *i2c, int reg, u8 value);
76 u8 (*getreg)(struct ocores_i2c_bus *i2c, int reg);
87 static void oc_setreg_8(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
89 writeb(value, i2c->base + (reg << i2c->reg_shift));
92 static void oc_setreg_16(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
94 writew(value, i2c
97 oc_setreg_32(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
102 oc_setreg_16be(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
107 oc_setreg_32be(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
112 oc_getreg_8(struct ocores_i2c_bus *i2c, int reg) argument
117 oc_getreg_16(struct ocores_i2c_bus *i2c, int reg) argument
122 oc_getreg_32(struct ocores_i2c_bus *i2c, int reg) argument
127 oc_getreg_16be(struct ocores_i2c_bus *i2c, int reg) argument
132 oc_getreg_32be(struct ocores_i2c_bus *i2c, int reg) argument
137 oc_setreg(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
142 oc_getreg(struct ocores_i2c_bus *i2c, int reg) argument
152 ocores_process(struct ocores_i2c_bus *i2c, u8 stat) argument
220 struct ocores_i2c_bus *i2c = dev_id; local
247 ocores_wait(struct ocores_i2c_bus *i2c, int reg, u8 mask, u8 val, const unsigned long msec) argument
276 ocores_poll_wait(struct ocores_i2c_bus *i2c) argument
315 ocores_process_polling(struct ocores_i2c_bus *i2c) argument
338 ocores_xfer_core(struct ocores_i2c_bus *i2c, struct i2c_msg *msgs, int num, bool polling) argument
437 oc_getreg_grlib(struct ocores_i2c_bus *i2c, int reg) argument
451 oc_setreg_grlib(struct ocores_i2c_bus *i2c, int reg, u8 value) argument
[all...]
H A Ds3c24x0_i2c.c21 #include <i2c.h>
29 * @param i2c- pointer to the appropriate i2c register bank.
35 static int WaitForXfer(struct s3c24x0_i2c *i2c) argument
40 if (readl(&i2c->iiccon) & I2CCON_IRPND)
41 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ?
48 static void read_write_byte(struct s3c24x0_i2c *i2c) argument
50 clrbits_le32(&i2c->iiccon, I2CCON_IRPND);
53 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) argument
71 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c
101 i2c_transfer(struct s3c24x0_i2c *i2c, unsigned char cmd_type, unsigned char chip, unsigned char addr[], unsigned char addr_len, unsigned char data[], unsigned short data_len) argument
227 struct s3c24x0_i2c *i2c = i2c_bus->regs; local
280 struct s3c24x0_i2c *i2c = i2c_bus->regs; local
[all...]
H A Dnx_i2c.c4 #include <i2c.h>
77 /* s5pxx18 i2c must be reset before enabled */
124 struct nx_i2c_regs *i2c = bus->regs; local
158 writel(delay, &i2c->iiclc);
167 struct nx_i2c_regs *i2c = bus->regs; local
196 &i2c->iiccon);
199 writel(0, &i2c->iicstat);
200 writel(0x00, &i2c->iicadd);
203 writel(I2CSTAT_MTM | I2CSTAT_RXTXEN, &i2c->iicstat);
229 bus->sda_delay = dev_read_s32_default(dev, "i2c
258 i2c_is_busy(struct nx_i2c_regs *i2c) argument
273 i2c_enable_irq(struct nx_i2c_regs *i2c) argument
283 i2c_clear_irq(struct nx_i2c_regs *i2c) argument
302 i2c_enable_ack(struct nx_i2c_regs *i2c) argument
313 struct nx_i2c_regs *i2c = bus->regs; local
345 wait_for_xfer(struct nx_i2c_regs *i2c) argument
359 i2c_transfer(struct nx_i2c_regs *i2c, uchar cmd_type, uchar chip_addr, uchar addr[], uchar addr_len, uchar data[], unsigned short data_len, uint seq) argument
475 struct nx_i2c_bus *i2c; local
512 struct nx_i2c_bus *i2c; local
545 struct nx_i2c_regs *i2c = bus->regs; local
[all...]
H A Dsynquacer_i2c.c13 #include <i2c.h>
125 struct synquacer_i2c *i2c = dev_get_priv(dev); local
129 if (readb(i2c->base + REG_BCR) & BCR_INT)
137 static int synquacer_i2c_xfer_start(struct synquacer_i2c *i2c, argument
142 writeb((addr << 1) | (read ? 1 : 0), i2c->base + REG_DAR);
144 bsr = readb(i2c->base + REG_BSR);
145 bcr = readb(i2c->base + REG_BCR);
151 writeb(bcr | BCR_SCC, i2c->base + REG_BCR);
156 writeb(bcr | BCR_MSS | BCR_INTE | BCR_BEIE, i2c->base + REG_BCR);
166 struct synquacer_i2c *i2c local
226 synquacer_i2c_hw_reset(struct synquacer_i2c *i2c) argument
245 struct synquacer_i2c *i2c = dev_get_priv(bus); local
252 struct synquacer_i2c *i2c = dev_get_priv(bus); local
309 struct synquacer_i2c *i2c = dev_get_priv(bus); local
[all...]
H A Dexynos_hs_i2c.c11 #include <i2c.h>
99 * @param i2c: pointer to the appropriate register bank
105 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) argument
110 u32 int_status = readl(&i2c->usi_int_stat);
113 u32 trans_status = readl(&i2c->usi_trans_status);
116 writel(int_status, &i2c->usi_int_stat);
229 struct exynos5_hsi2c *i2c = i2c_bus->hsregs; local
233 i2c_ctl = readl(&i2c->usi_ctl);
235 writel(i2c_ctl, &i2c->usi_ctl);
237 i2c_ctl = readl(&i2c
262 hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) argument
306 hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, u8 chip, u16 len, bool rx_transfer, bool issue_stop) argument
350 hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) argument
364 hsi2c_write(struct exynos5_hsi2c *i2c, unsigned char chip, unsigned char addr[], unsigned char alen, unsigned char data[], unsigned short len, bool issue_stop) argument
417 hsi2c_read(struct exynos5_hsi2c *i2c, unsigned char chip, unsigned char addr[], unsigned char alen, unsigned char data[], unsigned short len) argument
[all...]
H A DMakefile5 obj-$(CONFIG_$(SPL_)DM_I2C) += i2c-uclass.o
9 obj-$(CONFIG_$(SPL_)DM_I2C_GPIO) += i2c-gpio.o
17 obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o
18 obj-$(CONFIG_SYS_I2C_CA) += i2c-cortina.o
30 obj-$(CONFIG_SYS_I2C_MICROCHIP) += i2c-microchip.o
46 obj-$(CONFIG_SYS_I2C_SANDBOX) += sandbox_i2c.o i2c-emul-uclass.o
54 obj-$(CONFIG_SYS_I2C_UNIPHIER) += i2c-uniphier.o
55 obj-$(CONFIG_SYS_I2C_UNIPHIER_F) += i2c-uniphier-f.o
56 obj-$(CONFIG_SYS_I2C_VERSATILE) += i2c-versatile.o
H A Drk_i2c.c13 #include <i2c.h>
17 #include <asm/arch-rockchip/i2c.h>
23 /* i2c timerout */
27 /* rk i2c fifo max transfer bytes */
42 * @controller_type: i2c controller type
62 static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate) argument
67 /* First get i2c rate from pclk */
68 i2c_rate = clk_get_rate(&i2c->clk);
75 writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
77 debug("rk_i2c_set_clk: i2c rat
104 rk_i2c_send_start_bit(struct rk_i2c *i2c) argument
132 rk_i2c_send_stop_bit(struct rk_i2c *i2c) argument
160 rk_i2c_disable(struct rk_i2c *i2c) argument
165 rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, uchar *buf, uint b_len) argument
263 rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, uchar *buf, uint b_len) argument
344 struct rk_i2c *i2c = dev_get_priv(bus); local
372 struct rk_i2c *i2c = dev_get_priv(bus); local
[all...]
H A Dsandbox_i2c.c11 #include <i2c.h>
13 #include <asm/i2c.h>
49 struct dm_i2c_bus *i2c = dev_get_uclass_priv(bus); local
74 if (i2c->speed_hz > (is_read ? I2C_SPEED_FAST_RATE :
89 { .compatible = "sandbox,i2c" },
/u-boot/drivers/i2c/muxes/
H A DMakefile4 obj-$(CONFIG_I2C_ARB_GPIO_CHALLENGE) += i2c-arb-gpio-challenge.o
5 obj-$(CONFIG_I2C_MUX) += i2c-mux-uclass.o
7 obj-$(CONFIG_I2C_MUX_GPIO) += i2c-mux-gpio.o
/u-boot/post/drivers/
H A DMakefile6 obj-y += flash.o i2c.o memory.o rtc.o
/u-boot/board/starfive/visionfive2/
H A DMakefile8 obj-$(CONFIG_ID_EEPROM) += visionfive2-i2c-eeprom.o
/u-boot/drivers/tee/optee/
H A DMakefile5 obj-$(CONFIG_DM_I2C) += i2c.o
/u-boot/drivers/power/pmic/
H A Dpmic_pfuze3000.c9 #include <i2c.h>
26 p->hw.i2c.addr = CFG_POWER_PFUZE3000_I2C_ADDR;
27 p->hw.i2c.tx_num = 1;
H A Dpmic_ltc3676.c9 #include <i2c.h>
26 p->hw.i2c.addr = CFG_POWER_LTC3676_I2C_ADDR;
27 p->hw.i2c.tx_num = 1;
H A Dpmic_pfuze100.c9 #include <i2c.h>
26 p->hw.i2c.addr = CFG_POWER_PFUZE100_I2C_ADDR;
27 p->hw.i2c.tx_num = 1;
H A Dpmic_mc34vr500.c9 #include <i2c.h>
26 p->hw.i2c.addr = MC34VR500_I2C_ADDR;
27 p->hw.i2c.tx_num = 1;
H A Dpmic_pca9450.c8 #include <i2c.h>
26 p->hw.i2c.addr = addr;
27 p->hw.i2c.tx_num = 1;
/u-boot/board/sifive/unmatched/
H A DMakefile5 obj-$(CONFIG_ID_EEPROM) += hifive-platform-i2c-eeprom.o
/u-boot/drivers/tee/
H A DMakefile6 obj-$(CONFIG_OPTEE_TA_RPC_TEST) += optee/i2c.o
/u-boot/drivers/power/
H A Dpower_dialog.c27 p->hw.i2c.addr = CFG_SYS_DIALOG_PMIC_I2C_ADDR;
28 p->hw.i2c.tx_num = 1;
H A Dsy8106a.c7 #include <i2c.h>
/u-boot/board/freescale/common/
H A Dvsc3316_3308.h9 #include <i2c.h>
H A Di2c_common.c9 #include <i2c.h>
H A Di2c_mux.c9 #include <i2c.h>

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