Searched refs:hclk (Results 1 - 10 of 10) sorted by relevance

/u-boot/drivers/rng/
H A Djh7110_rng.c82 struct clk *hclk; member in struct:starfive_trng_plat
202 err = clk_enable(pdata->hclk);
227 clk_disable(pdata->hclk);
240 pdata->hclk = devm_clk_get(dev, "hclk");
241 if (IS_ERR(pdata->hclk))
/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_init.c1123 u32 tmp, hclk; local
1127 hclk = 84;
1140 hclk = 150;
1146 hclk = 165;
1150 hclk = 180;
1157 hclk = 200;
1162 hclk = 222;
1168 hclk = 250;
1174 hclk = 267;
1180 hclk
[all...]
H A Dddr3_dfs.c127 u32 hclk; local
129 get_target_freq(cpu_freq, &tmp, &hclk);
783 u32 hclk; local
785 get_target_freq(cpu_freq, &tmp, &hclk);
/u-boot/drivers/mtd/nand/raw/
H A Dlpc32xx_nand_slc.c116 uint32_t hclk = get_hclk_clk_rate(); local
131 TAC_W_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_WWIDTH) |
132 TAC_W_HOLD(hclk / CFG_LPC32XX_NAND_SLC_WHOLD) |
133 TAC_W_SETUP(hclk / CFG_LPC32XX_NAND_SLC_WSETUP) |
135 TAC_R_WIDTH(hclk / CFG_LPC32XX_NAND_SLC_RWIDTH) |
136 TAC_R_HOLD(hclk / CFG_LPC32XX_NAND_SLC_RHOLD) |
137 TAC_R_SETUP(hclk / CFG_LPC32XX_NAND_SLC_RSETUP),
H A Dstm32_fmc2_nand.c610 unsigned long hclk = clk_get_rate(&nfc->clk); local
611 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c213 unsigned long hclk; local
232 hclk = get_pll_clk(MPLL) / (hclk_sys_ratio + 1);
234 return hclk;
/u-boot/drivers/spi/
H A Drockchip_sfc.c175 struct clk hclk; member in struct:rockchip_sfc
244 ret = clk_get_by_index(bus, 1, &sfc->hclk);
260 ret = clk_enable(&sfc->hclk);
283 clk_disable(&sfc->hclk);
H A Dspi-aspeed-smc.c199 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no",
339 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no",
466 dev_dbg(dev, "found: %s, hclk: %d, max_clk: %d\n", found ? "yes" : "no",
1126 struct clk hclk; local
1144 ret = clk_get_by_index(bus, 0, &hclk);
1150 plat->hclk_rate = clk_get_rate(&hclk);
1154 dev_dbg(bus, "hclk = %dMHz, max_cs = %d\n",
/u-boot/board/menlo/m53menlo/
H A Dm53menlo.c172 static void enable_lvds_clock(struct display_info_t const *dev, const u8 hclk) argument
184 ret = mxc_set_clock(MXC_HCLK, hclk, MXC_LDB_CLK);
/u-boot/drivers/memory/
H A Dstm32-fmc2-ebi.c357 unsigned long hclk = clk_get_rate(&ebi->clk); local
358 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);

Completed in 141 milliseconds