1// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 2/* 3 * Copyright (C) STMicroelectronics 2019 4 * Author: Christophe Kerello <christophe.kerello@st.com> 5 */ 6 7#define LOG_CATEGORY UCLASS_MTD 8 9#include <common.h> 10#include <clk.h> 11#include <dm.h> 12#include <log.h> 13#include <nand.h> 14#include <reset.h> 15#include <asm/gpio.h> 16#include <dm/device_compat.h> 17#include <linux/bitfield.h> 18#include <linux/bitops.h> 19#include <linux/delay.h> 20#include <linux/err.h> 21#include <linux/iopoll.h> 22#include <linux/ioport.h> 23#include <linux/mtd/rawnand.h> 24#include <linux/printk.h> 25#include <linux/time.h> 26 27/* Bad block marker length */ 28#define FMC2_BBM_LEN 2 29 30/* ECC step size */ 31#define FMC2_ECC_STEP_SIZE 512 32 33/* Command delay */ 34#define FMC2_RB_DELAY_US 30 35 36/* Max chip enable */ 37#define FMC2_MAX_CE 4 38 39/* Timings */ 40#define FMC2_THIZ 1 41#define FMC2_TIO 8000 42#define FMC2_TSYNC 3000 43#define FMC2_PCR_TIMING_MASK 0xf 44#define FMC2_PMEM_PATT_TIMING_MASK 0xff 45 46/* FMC2 Controller Registers */ 47#define FMC2_BCR1 0x0 48#define FMC2_PCR 0x80 49#define FMC2_SR 0x84 50#define FMC2_PMEM 0x88 51#define FMC2_PATT 0x8c 52#define FMC2_HECCR 0x94 53#define FMC2_BCHISR 0x254 54#define FMC2_BCHICR 0x258 55#define FMC2_BCHPBR1 0x260 56#define FMC2_BCHPBR2 0x264 57#define FMC2_BCHPBR3 0x268 58#define FMC2_BCHPBR4 0x26c 59#define FMC2_BCHDSR0 0x27c 60#define FMC2_BCHDSR1 0x280 61#define FMC2_BCHDSR2 0x284 62#define FMC2_BCHDSR3 0x288 63#define FMC2_BCHDSR4 0x28c 64 65/* Register: FMC2_BCR1 */ 66#define FMC2_BCR1_FMC2EN BIT(31) 67 68/* Register: FMC2_PCR */ 69#define FMC2_PCR_PWAITEN BIT(1) 70#define FMC2_PCR_PBKEN BIT(2) 71#define FMC2_PCR_PWID GENMASK(5, 4) 72#define FMC2_PCR_PWID_BUSWIDTH_8 0 73#define FMC2_PCR_PWID_BUSWIDTH_16 1 74#define FMC2_PCR_ECCEN BIT(6) 75#define FMC2_PCR_ECCALG BIT(8) 76#define FMC2_PCR_TCLR GENMASK(12, 9) 77#define FMC2_PCR_TCLR_DEFAULT 0xf 78#define FMC2_PCR_TAR GENMASK(16, 13) 79#define FMC2_PCR_TAR_DEFAULT 0xf 80#define FMC2_PCR_ECCSS GENMASK(19, 17) 81#define FMC2_PCR_ECCSS_512 1 82#define FMC2_PCR_ECCSS_2048 3 83#define FMC2_PCR_BCHECC BIT(24) 84#define FMC2_PCR_WEN BIT(25) 85 86/* Register: FMC2_SR */ 87#define FMC2_SR_NWRF BIT(6) 88 89/* Register: FMC2_PMEM */ 90#define FMC2_PMEM_MEMSET GENMASK(7, 0) 91#define FMC2_PMEM_MEMWAIT GENMASK(15, 8) 92#define FMC2_PMEM_MEMHOLD GENMASK(23, 16) 93#define FMC2_PMEM_MEMHIZ GENMASK(31, 24) 94#define FMC2_PMEM_DEFAULT 0x0a0a0a0a 95 96/* Register: FMC2_PATT */ 97#define FMC2_PATT_ATTSET GENMASK(7, 0) 98#define FMC2_PATT_ATTWAIT GENMASK(15, 8) 99#define FMC2_PATT_ATTHOLD GENMASK(23, 16) 100#define FMC2_PATT_ATTHIZ GENMASK(31, 24) 101#define FMC2_PATT_DEFAULT 0x0a0a0a0a 102 103/* Register: FMC2_BCHISR */ 104#define FMC2_BCHISR_DERF BIT(1) 105#define FMC2_BCHISR_EPBRF BIT(4) 106 107/* Register: FMC2_BCHICR */ 108#define FMC2_BCHICR_CLEAR_IRQ GENMASK(4, 0) 109 110/* Register: FMC2_BCHDSR0 */ 111#define FMC2_BCHDSR0_DUE BIT(0) 112#define FMC2_BCHDSR0_DEF BIT(1) 113#define FMC2_BCHDSR0_DEN GENMASK(7, 4) 114 115/* Register: FMC2_BCHDSR1 */ 116#define FMC2_BCHDSR1_EBP1 GENMASK(12, 0) 117#define FMC2_BCHDSR1_EBP2 GENMASK(28, 16) 118 119/* Register: FMC2_BCHDSR2 */ 120#define FMC2_BCHDSR2_EBP3 GENMASK(12, 0) 121#define FMC2_BCHDSR2_EBP4 GENMASK(28, 16) 122 123/* Register: FMC2_BCHDSR3 */ 124#define FMC2_BCHDSR3_EBP5 GENMASK(12, 0) 125#define FMC2_BCHDSR3_EBP6 GENMASK(28, 16) 126 127/* Register: FMC2_BCHDSR4 */ 128#define FMC2_BCHDSR4_EBP7 GENMASK(12, 0) 129#define FMC2_BCHDSR4_EBP8 GENMASK(28, 16) 130 131#define FMC2_TIMEOUT_5S 5000000 132 133enum stm32_fmc2_ecc { 134 FMC2_ECC_HAM = 1, 135 FMC2_ECC_BCH4 = 4, 136 FMC2_ECC_BCH8 = 8 137}; 138 139struct stm32_fmc2_timings { 140 u8 tclr; 141 u8 tar; 142 u8 thiz; 143 u8 twait; 144 u8 thold_mem; 145 u8 tset_mem; 146 u8 thold_att; 147 u8 tset_att; 148}; 149 150struct stm32_fmc2_nand { 151 struct nand_chip chip; 152 struct stm32_fmc2_timings timings; 153 struct gpio_desc wp_gpio; 154 int ncs; 155 int cs_used[FMC2_MAX_CE]; 156}; 157 158static inline struct stm32_fmc2_nand *to_fmc2_nand(struct nand_chip *chip) 159{ 160 return container_of(chip, struct stm32_fmc2_nand, chip); 161} 162 163struct stm32_fmc2_nfc_data { 164 int max_ncs; 165 struct udevice *(*get_cdev)(struct udevice *dev); 166}; 167 168struct stm32_fmc2_nfc { 169 struct nand_hw_control base; 170 struct stm32_fmc2_nand nand; 171 struct nand_ecclayout ecclayout; 172 fdt_addr_t io_base; 173 fdt_addr_t data_base[FMC2_MAX_CE]; 174 fdt_addr_t cmd_base[FMC2_MAX_CE]; 175 fdt_addr_t addr_base[FMC2_MAX_CE]; 176 struct clk clk; 177 const struct stm32_fmc2_nfc_data *data; 178 179 u8 cs_assigned; 180 int cs_sel; 181}; 182 183static inline struct stm32_fmc2_nfc *to_stm32_nfc(struct nand_hw_control *base) 184{ 185 return container_of(base, struct stm32_fmc2_nfc, base); 186} 187 188static void stm32_fmc2_nfc_timings_init(struct nand_chip *chip) 189{ 190 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 191 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 192 struct stm32_fmc2_timings *timings = &nand->timings; 193 u32 pmem, patt; 194 195 /* Set tclr/tar timings */ 196 clrsetbits_le32(nfc->io_base + FMC2_PCR, 197 FMC2_PCR_TCLR | FMC2_PCR_TAR, 198 FIELD_PREP(FMC2_PCR_TCLR, timings->tclr) | 199 FIELD_PREP(FMC2_PCR_TAR, timings->tar)); 200 201 /* Set tset/twait/thold/thiz timings in common bank */ 202 pmem = FIELD_PREP(FMC2_PMEM_MEMSET, timings->tset_mem); 203 pmem |= FIELD_PREP(FMC2_PMEM_MEMWAIT, timings->twait); 204 pmem |= FIELD_PREP(FMC2_PMEM_MEMHOLD, timings->thold_mem); 205 pmem |= FIELD_PREP(FMC2_PMEM_MEMHIZ, timings->thiz); 206 writel(pmem, nfc->io_base + FMC2_PMEM); 207 208 /* Set tset/twait/thold/thiz timings in attribut bank */ 209 patt = FIELD_PREP(FMC2_PATT_ATTSET, timings->tset_att); 210 patt |= FIELD_PREP(FMC2_PATT_ATTWAIT, timings->twait); 211 patt |= FIELD_PREP(FMC2_PATT_ATTHOLD, timings->thold_att); 212 patt |= FIELD_PREP(FMC2_PATT_ATTHIZ, timings->thiz); 213 writel(patt, nfc->io_base + FMC2_PATT); 214} 215 216static void stm32_fmc2_nfc_setup(struct nand_chip *chip) 217{ 218 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 219 u32 pcr = 0, pcr_mask; 220 221 /* Configure ECC algorithm (default configuration is Hamming) */ 222 pcr_mask = FMC2_PCR_ECCALG; 223 pcr_mask |= FMC2_PCR_BCHECC; 224 if (chip->ecc.strength == FMC2_ECC_BCH8) { 225 pcr |= FMC2_PCR_ECCALG; 226 pcr |= FMC2_PCR_BCHECC; 227 } else if (chip->ecc.strength == FMC2_ECC_BCH4) { 228 pcr |= FMC2_PCR_ECCALG; 229 } 230 231 /* Set buswidth */ 232 pcr_mask |= FMC2_PCR_PWID; 233 if (chip->options & NAND_BUSWIDTH_16) 234 pcr |= FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16); 235 236 /* Set ECC sector size */ 237 pcr_mask |= FMC2_PCR_ECCSS; 238 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_512); 239 240 clrsetbits_le32(nfc->io_base + FMC2_PCR, pcr_mask, pcr); 241} 242 243static void stm32_fmc2_nfc_select_chip(struct mtd_info *mtd, int chipnr) 244{ 245 struct nand_chip *chip = mtd_to_nand(mtd); 246 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 247 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 248 249 if (chipnr < 0 || chipnr >= nand->ncs) 250 return; 251 252 if (nand->cs_used[chipnr] == nfc->cs_sel) 253 return; 254 255 nfc->cs_sel = nand->cs_used[chipnr]; 256 chip->IO_ADDR_R = (void __iomem *)nfc->data_base[nfc->cs_sel]; 257 chip->IO_ADDR_W = (void __iomem *)nfc->data_base[nfc->cs_sel]; 258 259 stm32_fmc2_nfc_setup(chip); 260 stm32_fmc2_nfc_timings_init(chip); 261} 262 263static void stm32_fmc2_nfc_set_buswidth_16(struct stm32_fmc2_nfc *nfc, 264 bool set) 265{ 266 u32 pcr; 267 268 pcr = set ? FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_16) : 269 FIELD_PREP(FMC2_PCR_PWID, FMC2_PCR_PWID_BUSWIDTH_8); 270 271 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_PWID, pcr); 272} 273 274static void stm32_fmc2_nfc_set_ecc(struct stm32_fmc2_nfc *nfc, bool enable) 275{ 276 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_ECCEN, 277 enable ? FMC2_PCR_ECCEN : 0); 278} 279 280static void stm32_fmc2_nfc_clear_bch_irq(struct stm32_fmc2_nfc *nfc) 281{ 282 writel(FMC2_BCHICR_CLEAR_IRQ, nfc->io_base + FMC2_BCHICR); 283} 284 285static void stm32_fmc2_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, 286 unsigned int ctrl) 287{ 288 struct nand_chip *chip = mtd_to_nand(mtd); 289 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 290 291 if (cmd == NAND_CMD_NONE) 292 return; 293 294 if (ctrl & NAND_CLE) { 295 writeb(cmd, nfc->cmd_base[nfc->cs_sel]); 296 return; 297 } 298 299 writeb(cmd, nfc->addr_base[nfc->cs_sel]); 300} 301 302/* 303 * Enable ECC logic and reset syndrome/parity bits previously calculated 304 * Syndrome/parity bits is cleared by setting the ECCEN bit to 0 305 */ 306static void stm32_fmc2_nfc_hwctl(struct mtd_info *mtd, int mode) 307{ 308 struct nand_chip *chip = mtd_to_nand(mtd); 309 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 310 311 stm32_fmc2_nfc_set_ecc(nfc, false); 312 313 if (chip->ecc.strength != FMC2_ECC_HAM) { 314 clrsetbits_le32(nfc->io_base + FMC2_PCR, FMC2_PCR_WEN, 315 mode == NAND_ECC_WRITE ? FMC2_PCR_WEN : 0); 316 317 stm32_fmc2_nfc_clear_bch_irq(nfc); 318 } 319 320 stm32_fmc2_nfc_set_ecc(nfc, true); 321} 322 323/* 324 * ECC Hamming calculation 325 * ECC is 3 bytes for 512 bytes of data (supports error correction up to 326 * max of 1-bit) 327 */ 328static int stm32_fmc2_nfc_ham_calculate(struct mtd_info *mtd, const u8 *data, 329 u8 *ecc) 330{ 331 struct nand_chip *chip = mtd_to_nand(mtd); 332 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 333 u32 heccr, sr; 334 int ret; 335 336 ret = readl_poll_timeout(nfc->io_base + FMC2_SR, sr, 337 sr & FMC2_SR_NWRF, FMC2_TIMEOUT_5S); 338 if (ret < 0) { 339 log_err("Ham timeout\n"); 340 return ret; 341 } 342 343 heccr = readl(nfc->io_base + FMC2_HECCR); 344 345 ecc[0] = heccr; 346 ecc[1] = heccr >> 8; 347 ecc[2] = heccr >> 16; 348 349 stm32_fmc2_nfc_set_ecc(nfc, false); 350 351 return 0; 352} 353 354static int stm32_fmc2_nfc_ham_correct(struct mtd_info *mtd, u8 *dat, 355 u8 *read_ecc, u8 *calc_ecc) 356{ 357 u8 bit_position = 0, b0, b1, b2; 358 u32 byte_addr = 0, b; 359 u32 i, shifting = 1; 360 361 /* Indicate which bit and byte is faulty (if any) */ 362 b0 = read_ecc[0] ^ calc_ecc[0]; 363 b1 = read_ecc[1] ^ calc_ecc[1]; 364 b2 = read_ecc[2] ^ calc_ecc[2]; 365 b = b0 | (b1 << 8) | (b2 << 16); 366 367 /* No errors */ 368 if (likely(!b)) 369 return 0; 370 371 /* Calculate bit position */ 372 for (i = 0; i < 3; i++) { 373 switch (b % 4) { 374 case 2: 375 bit_position += shifting; 376 case 1: 377 break; 378 default: 379 return -EBADMSG; 380 } 381 shifting <<= 1; 382 b >>= 2; 383 } 384 385 /* Calculate byte position */ 386 shifting = 1; 387 for (i = 0; i < 9; i++) { 388 switch (b % 4) { 389 case 2: 390 byte_addr += shifting; 391 case 1: 392 break; 393 default: 394 return -EBADMSG; 395 } 396 shifting <<= 1; 397 b >>= 2; 398 } 399 400 /* Flip the bit */ 401 dat[byte_addr] ^= (1 << bit_position); 402 403 return 1; 404} 405 406/* 407 * ECC BCH calculation and correction 408 * ECC is 7/13 bytes for 512 bytes of data (supports error correction up to 409 * max of 4-bit/8-bit) 410 */ 411 412static int stm32_fmc2_nfc_bch_calculate(struct mtd_info *mtd, const u8 *data, 413 u8 *ecc) 414{ 415 struct nand_chip *chip = mtd_to_nand(mtd); 416 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 417 u32 bchpbr, bchisr; 418 int ret; 419 420 /* Wait until the BCH code is ready */ 421 ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr, 422 bchisr & FMC2_BCHISR_EPBRF, FMC2_TIMEOUT_5S); 423 if (ret < 0) { 424 log_err("Bch timeout\n"); 425 return ret; 426 } 427 428 /* Read parity bits */ 429 bchpbr = readl(nfc->io_base + FMC2_BCHPBR1); 430 ecc[0] = bchpbr; 431 ecc[1] = bchpbr >> 8; 432 ecc[2] = bchpbr >> 16; 433 ecc[3] = bchpbr >> 24; 434 435 bchpbr = readl(nfc->io_base + FMC2_BCHPBR2); 436 ecc[4] = bchpbr; 437 ecc[5] = bchpbr >> 8; 438 ecc[6] = bchpbr >> 16; 439 440 if (chip->ecc.strength == FMC2_ECC_BCH8) { 441 ecc[7] = bchpbr >> 24; 442 443 bchpbr = readl(nfc->io_base + FMC2_BCHPBR3); 444 ecc[8] = bchpbr; 445 ecc[9] = bchpbr >> 8; 446 ecc[10] = bchpbr >> 16; 447 ecc[11] = bchpbr >> 24; 448 449 bchpbr = readl(nfc->io_base + FMC2_BCHPBR4); 450 ecc[12] = bchpbr; 451 } 452 453 stm32_fmc2_nfc_set_ecc(nfc, false); 454 455 return 0; 456} 457 458static int stm32_fmc2_nfc_bch_correct(struct mtd_info *mtd, u8 *dat, 459 u8 *read_ecc, u8 *calc_ecc) 460{ 461 struct nand_chip *chip = mtd_to_nand(mtd); 462 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 463 u32 bchdsr0, bchdsr1, bchdsr2, bchdsr3, bchdsr4, bchisr; 464 u16 pos[8]; 465 int i, ret, den, eccsize = chip->ecc.size; 466 unsigned int nb_errs = 0; 467 468 /* Wait until the decoding error is ready */ 469 ret = readl_poll_timeout(nfc->io_base + FMC2_BCHISR, bchisr, 470 bchisr & FMC2_BCHISR_DERF, FMC2_TIMEOUT_5S); 471 if (ret < 0) { 472 log_err("Bch timeout\n"); 473 return ret; 474 } 475 476 bchdsr0 = readl(nfc->io_base + FMC2_BCHDSR0); 477 bchdsr1 = readl(nfc->io_base + FMC2_BCHDSR1); 478 bchdsr2 = readl(nfc->io_base + FMC2_BCHDSR2); 479 bchdsr3 = readl(nfc->io_base + FMC2_BCHDSR3); 480 bchdsr4 = readl(nfc->io_base + FMC2_BCHDSR4); 481 482 stm32_fmc2_nfc_set_ecc(nfc, false); 483 484 /* No errors found */ 485 if (likely(!(bchdsr0 & FMC2_BCHDSR0_DEF))) 486 return 0; 487 488 /* Too many errors detected */ 489 if (unlikely(bchdsr0 & FMC2_BCHDSR0_DUE)) 490 return -EBADMSG; 491 492 pos[0] = FIELD_GET(FMC2_BCHDSR1_EBP1, bchdsr1); 493 pos[1] = FIELD_GET(FMC2_BCHDSR1_EBP2, bchdsr1); 494 pos[2] = FIELD_GET(FMC2_BCHDSR2_EBP3, bchdsr2); 495 pos[3] = FIELD_GET(FMC2_BCHDSR2_EBP4, bchdsr2); 496 pos[4] = FIELD_GET(FMC2_BCHDSR3_EBP5, bchdsr3); 497 pos[5] = FIELD_GET(FMC2_BCHDSR3_EBP6, bchdsr3); 498 pos[6] = FIELD_GET(FMC2_BCHDSR4_EBP7, bchdsr4); 499 pos[7] = FIELD_GET(FMC2_BCHDSR4_EBP8, bchdsr4); 500 501 den = FIELD_GET(FMC2_BCHDSR0_DEN, bchdsr0); 502 for (i = 0; i < den; i++) { 503 if (pos[i] < eccsize * 8) { 504 __change_bit(pos[i], (unsigned long *)dat); 505 nb_errs++; 506 } 507 } 508 509 return nb_errs; 510} 511 512static int stm32_fmc2_nfc_read_page(struct mtd_info *mtd, 513 struct nand_chip *chip, u8 *buf, 514 int oob_required, int page) 515{ 516 int i, s, stat, eccsize = chip->ecc.size; 517 int eccbytes = chip->ecc.bytes; 518 int eccsteps = chip->ecc.steps; 519 int eccstrength = chip->ecc.strength; 520 u8 *p = buf; 521 u8 *ecc_calc = chip->buffers->ecccalc; 522 u8 *ecc_code = chip->buffers->ecccode; 523 unsigned int max_bitflips = 0; 524 525 for (i = mtd->writesize + FMC2_BBM_LEN, s = 0; s < eccsteps; 526 s++, i += eccbytes, p += eccsize) { 527 chip->ecc.hwctl(mtd, NAND_ECC_READ); 528 529 /* Read the nand page sector (512 bytes) */ 530 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, s * eccsize, -1); 531 chip->read_buf(mtd, p, eccsize); 532 533 /* Read the corresponding ECC bytes */ 534 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, i, -1); 535 chip->read_buf(mtd, ecc_code, eccbytes); 536 537 /* Correct the data */ 538 stat = chip->ecc.correct(mtd, p, ecc_code, ecc_calc); 539 if (stat == -EBADMSG) 540 /* Check for empty pages with bitflips */ 541 stat = nand_check_erased_ecc_chunk(p, eccsize, 542 ecc_code, eccbytes, 543 NULL, 0, 544 eccstrength); 545 546 if (stat < 0) { 547 mtd->ecc_stats.failed++; 548 } else { 549 mtd->ecc_stats.corrected += stat; 550 max_bitflips = max_t(unsigned int, max_bitflips, stat); 551 } 552 } 553 554 /* Read oob */ 555 if (oob_required) { 556 chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1); 557 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize); 558 } 559 560 return max_bitflips; 561} 562 563static void stm32_fmc2_nfc_init(struct stm32_fmc2_nfc *nfc, bool has_parent) 564{ 565 u32 pcr = readl(nfc->io_base + FMC2_PCR); 566 567 /* Set CS used to undefined */ 568 nfc->cs_sel = -1; 569 570 /* Enable wait feature and nand flash memory bank */ 571 pcr |= FMC2_PCR_PWAITEN; 572 pcr |= FMC2_PCR_PBKEN; 573 574 /* Set buswidth to 8 bits mode for identification */ 575 pcr &= ~FMC2_PCR_PWID; 576 577 /* ECC logic is disabled */ 578 pcr &= ~FMC2_PCR_ECCEN; 579 580 /* Default mode */ 581 pcr &= ~FMC2_PCR_ECCALG; 582 pcr &= ~FMC2_PCR_BCHECC; 583 pcr &= ~FMC2_PCR_WEN; 584 585 /* Set default ECC sector size */ 586 pcr &= ~FMC2_PCR_ECCSS; 587 pcr |= FIELD_PREP(FMC2_PCR_ECCSS, FMC2_PCR_ECCSS_2048); 588 589 /* Set default tclr/tar timings */ 590 pcr &= ~FMC2_PCR_TCLR; 591 pcr |= FIELD_PREP(FMC2_PCR_TCLR, FMC2_PCR_TCLR_DEFAULT); 592 pcr &= ~FMC2_PCR_TAR; 593 pcr |= FIELD_PREP(FMC2_PCR_TAR, FMC2_PCR_TAR_DEFAULT); 594 595 /* Enable FMC2 controller */ 596 if (!has_parent) 597 setbits_le32(nfc->io_base + FMC2_BCR1, FMC2_BCR1_FMC2EN); 598 599 writel(pcr, nfc->io_base + FMC2_PCR); 600 writel(FMC2_PMEM_DEFAULT, nfc->io_base + FMC2_PMEM); 601 writel(FMC2_PATT_DEFAULT, nfc->io_base + FMC2_PATT); 602} 603 604static void stm32_fmc2_nfc_calc_timings(struct nand_chip *chip, 605 const struct nand_sdr_timings *sdrt) 606{ 607 struct stm32_fmc2_nfc *nfc = to_stm32_nfc(chip->controller); 608 struct stm32_fmc2_nand *nand = to_fmc2_nand(chip); 609 struct stm32_fmc2_timings *tims = &nand->timings; 610 unsigned long hclk = clk_get_rate(&nfc->clk); 611 unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000); 612 unsigned long timing, tar, tclr, thiz, twait; 613 unsigned long tset_mem, tset_att, thold_mem, thold_att; 614 615 tar = max_t(unsigned long, hclkp, sdrt->tAR_min); 616 timing = DIV_ROUND_UP(tar, hclkp) - 1; 617 tims->tar = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); 618 619 tclr = max_t(unsigned long, hclkp, sdrt->tCLR_min); 620 timing = DIV_ROUND_UP(tclr, hclkp) - 1; 621 tims->tclr = min_t(unsigned long, timing, FMC2_PCR_TIMING_MASK); 622 623 tims->thiz = FMC2_THIZ; 624 thiz = (tims->thiz + 1) * hclkp; 625 626 /* 627 * tWAIT > tRP 628 * tWAIT > tWP 629 * tWAIT > tREA + tIO 630 */ 631 twait = max_t(unsigned long, hclkp, sdrt->tRP_min); 632 twait = max_t(unsigned long, twait, sdrt->tWP_min); 633 twait = max_t(unsigned long, twait, sdrt->tREA_max + FMC2_TIO); 634 timing = DIV_ROUND_UP(twait, hclkp); 635 tims->twait = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 636 637 /* 638 * tSETUP_MEM > tCS - tWAIT 639 * tSETUP_MEM > tALS - tWAIT 640 * tSETUP_MEM > tDS - (tWAIT - tHIZ) 641 */ 642 tset_mem = hclkp; 643 if (sdrt->tCS_min > twait && (tset_mem < sdrt->tCS_min - twait)) 644 tset_mem = sdrt->tCS_min - twait; 645 if (sdrt->tALS_min > twait && (tset_mem < sdrt->tALS_min - twait)) 646 tset_mem = sdrt->tALS_min - twait; 647 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 648 (tset_mem < sdrt->tDS_min - (twait - thiz))) 649 tset_mem = sdrt->tDS_min - (twait - thiz); 650 timing = DIV_ROUND_UP(tset_mem, hclkp); 651 tims->tset_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 652 653 /* 654 * tHOLD_MEM > tCH 655 * tHOLD_MEM > tREH - tSETUP_MEM 656 * tHOLD_MEM > max(tRC, tWC) - (tSETUP_MEM + tWAIT) 657 */ 658 thold_mem = max_t(unsigned long, hclkp, sdrt->tCH_min); 659 if (sdrt->tREH_min > tset_mem && 660 (thold_mem < sdrt->tREH_min - tset_mem)) 661 thold_mem = sdrt->tREH_min - tset_mem; 662 if ((sdrt->tRC_min > tset_mem + twait) && 663 (thold_mem < sdrt->tRC_min - (tset_mem + twait))) 664 thold_mem = sdrt->tRC_min - (tset_mem + twait); 665 if ((sdrt->tWC_min > tset_mem + twait) && 666 (thold_mem < sdrt->tWC_min - (tset_mem + twait))) 667 thold_mem = sdrt->tWC_min - (tset_mem + twait); 668 timing = DIV_ROUND_UP(thold_mem, hclkp); 669 tims->thold_mem = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 670 671 /* 672 * tSETUP_ATT > tCS - tWAIT 673 * tSETUP_ATT > tCLS - tWAIT 674 * tSETUP_ATT > tALS - tWAIT 675 * tSETUP_ATT > tRHW - tHOLD_MEM 676 * tSETUP_ATT > tDS - (tWAIT - tHIZ) 677 */ 678 tset_att = hclkp; 679 if (sdrt->tCS_min > twait && (tset_att < sdrt->tCS_min - twait)) 680 tset_att = sdrt->tCS_min - twait; 681 if (sdrt->tCLS_min > twait && (tset_att < sdrt->tCLS_min - twait)) 682 tset_att = sdrt->tCLS_min - twait; 683 if (sdrt->tALS_min > twait && (tset_att < sdrt->tALS_min - twait)) 684 tset_att = sdrt->tALS_min - twait; 685 if (sdrt->tRHW_min > thold_mem && 686 (tset_att < sdrt->tRHW_min - thold_mem)) 687 tset_att = sdrt->tRHW_min - thold_mem; 688 if (twait > thiz && (sdrt->tDS_min > twait - thiz) && 689 (tset_att < sdrt->tDS_min - (twait - thiz))) 690 tset_att = sdrt->tDS_min - (twait - thiz); 691 timing = DIV_ROUND_UP(tset_att, hclkp); 692 tims->tset_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 693 694 /* 695 * tHOLD_ATT > tALH 696 * tHOLD_ATT > tCH 697 * tHOLD_ATT > tCLH 698 * tHOLD_ATT > tCOH 699 * tHOLD_ATT > tDH 700 * tHOLD_ATT > tWB + tIO + tSYNC - tSETUP_MEM 701 * tHOLD_ATT > tADL - tSETUP_MEM 702 * tHOLD_ATT > tWH - tSETUP_MEM 703 * tHOLD_ATT > tWHR - tSETUP_MEM 704 * tHOLD_ATT > tRC - (tSETUP_ATT + tWAIT) 705 * tHOLD_ATT > tWC - (tSETUP_ATT + tWAIT) 706 */ 707 thold_att = max_t(unsigned long, hclkp, sdrt->tALH_min); 708 thold_att = max_t(unsigned long, thold_att, sdrt->tCH_min); 709 thold_att = max_t(unsigned long, thold_att, sdrt->tCLH_min); 710 thold_att = max_t(unsigned long, thold_att, sdrt->tCOH_min); 711 thold_att = max_t(unsigned long, thold_att, sdrt->tDH_min); 712 if ((sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC > tset_mem) && 713 (thold_att < sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem)) 714 thold_att = sdrt->tWB_max + FMC2_TIO + FMC2_TSYNC - tset_mem; 715 if (sdrt->tADL_min > tset_mem && 716 (thold_att < sdrt->tADL_min - tset_mem)) 717 thold_att = sdrt->tADL_min - tset_mem; 718 if (sdrt->tWH_min > tset_mem && 719 (thold_att < sdrt->tWH_min - tset_mem)) 720 thold_att = sdrt->tWH_min - tset_mem; 721 if (sdrt->tWHR_min > tset_mem && 722 (thold_att < sdrt->tWHR_min - tset_mem)) 723 thold_att = sdrt->tWHR_min - tset_mem; 724 if ((sdrt->tRC_min > tset_att + twait) && 725 (thold_att < sdrt->tRC_min - (tset_att + twait))) 726 thold_att = sdrt->tRC_min - (tset_att + twait); 727 if ((sdrt->tWC_min > tset_att + twait) && 728 (thold_att < sdrt->tWC_min - (tset_att + twait))) 729 thold_att = sdrt->tWC_min - (tset_att + twait); 730 timing = DIV_ROUND_UP(thold_att, hclkp); 731 tims->thold_att = clamp_val(timing, 1, FMC2_PMEM_PATT_TIMING_MASK); 732} 733 734static int stm32_fmc2_nfc_setup_interface(struct mtd_info *mtd, int chipnr, 735 const struct nand_data_interface *cf) 736{ 737 struct nand_chip *chip = mtd_to_nand(mtd); 738 const struct nand_sdr_timings *sdrt; 739 740 sdrt = nand_get_sdr_timings(cf); 741 if (IS_ERR(sdrt)) 742 return PTR_ERR(sdrt); 743 744 if (sdrt->tRC_min < 30000) 745 return -EOPNOTSUPP; 746 747 if (chipnr == NAND_DATA_IFACE_CHECK_ONLY) 748 return 0; 749 750 stm32_fmc2_nfc_calc_timings(chip, sdrt); 751 stm32_fmc2_nfc_timings_init(chip); 752 753 return 0; 754} 755 756static void stm32_fmc2_nfc_nand_callbacks_setup(struct nand_chip *chip) 757{ 758 chip->ecc.hwctl = stm32_fmc2_nfc_hwctl; 759 760 /* 761 * Specific callbacks to read/write a page depending on 762 * the algo used (Hamming, BCH). 763 */ 764 if (chip->ecc.strength == FMC2_ECC_HAM) { 765 /* Hamming is used */ 766 chip->ecc.calculate = stm32_fmc2_nfc_ham_calculate; 767 chip->ecc.correct = stm32_fmc2_nfc_ham_correct; 768 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 4 : 3; 769 chip->ecc.options |= NAND_ECC_GENERIC_ERASED_CHECK; 770 return; 771 } 772 773 /* BCH is used */ 774 chip->ecc.read_page = stm32_fmc2_nfc_read_page; 775 chip->ecc.calculate = stm32_fmc2_nfc_bch_calculate; 776 chip->ecc.correct = stm32_fmc2_nfc_bch_correct; 777 778 if (chip->ecc.strength == FMC2_ECC_BCH8) 779 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 14 : 13; 780 else 781 chip->ecc.bytes = chip->options & NAND_BUSWIDTH_16 ? 8 : 7; 782} 783 784static int stm32_fmc2_nfc_calc_ecc_bytes(int step_size, int strength) 785{ 786 /* Hamming */ 787 if (strength == FMC2_ECC_HAM) 788 return 4; 789 790 /* BCH8 */ 791 if (strength == FMC2_ECC_BCH8) 792 return 14; 793 794 /* BCH4 */ 795 return 8; 796} 797 798NAND_ECC_CAPS_SINGLE(stm32_fmc2_nfc_ecc_caps, stm32_fmc2_nfc_calc_ecc_bytes, 799 FMC2_ECC_STEP_SIZE, 800 FMC2_ECC_HAM, FMC2_ECC_BCH4, FMC2_ECC_BCH8); 801 802static int stm32_fmc2_nfc_parse_child(struct stm32_fmc2_nfc *nfc, ofnode node) 803{ 804 struct stm32_fmc2_nand *nand = &nfc->nand; 805 u32 cs[FMC2_MAX_CE]; 806 int ret, i; 807 808 if (!ofnode_get_property(node, "reg", &nand->ncs)) 809 return -EINVAL; 810 811 nand->ncs /= sizeof(u32); 812 if (!nand->ncs) { 813 log_err("Invalid reg property size\n"); 814 return -EINVAL; 815 } 816 817 ret = ofnode_read_u32_array(node, "reg", cs, nand->ncs); 818 if (ret < 0) { 819 log_err("Could not retrieve reg property\n"); 820 return -EINVAL; 821 } 822 823 for (i = 0; i < nand->ncs; i++) { 824 if (cs[i] >= nfc->data->max_ncs) { 825 log_err("Invalid reg value: %d\n", nand->cs_used[i]); 826 return -EINVAL; 827 } 828 829 if (nfc->cs_assigned & BIT(cs[i])) { 830 log_err("Cs already assigned: %d\n", nand->cs_used[i]); 831 return -EINVAL; 832 } 833 834 nfc->cs_assigned |= BIT(cs[i]); 835 nand->cs_used[i] = cs[i]; 836 } 837 838 gpio_request_by_name_nodev(node, "wp-gpios", 0, &nand->wp_gpio, 839 GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE); 840 841 nand->chip.flash_node = node; 842 843 return 0; 844} 845 846static int stm32_fmc2_nfc_parse_dt(struct udevice *dev, 847 struct stm32_fmc2_nfc *nfc) 848{ 849 ofnode child; 850 int ret, nchips = 0; 851 852 dev_for_each_subnode(child, dev) 853 nchips++; 854 855 if (!nchips) { 856 log_err("NAND chip not defined\n"); 857 return -EINVAL; 858 } 859 860 if (nchips > 1) { 861 log_err("Too many NAND chips defined\n"); 862 return -EINVAL; 863 } 864 865 dev_for_each_subnode(child, dev) { 866 ret = stm32_fmc2_nfc_parse_child(nfc, child); 867 if (ret) 868 return ret; 869 } 870 871 return 0; 872} 873 874static struct udevice *stm32_fmc2_nfc_get_cdev(struct udevice *dev) 875{ 876 struct udevice *pdev = dev_get_parent(dev); 877 struct udevice *cdev = NULL; 878 bool ebi_found = false; 879 880 if (pdev && ofnode_device_is_compatible(dev_ofnode(pdev), 881 "st,stm32mp1-fmc2-ebi")) 882 ebi_found = true; 883 884 if (ofnode_device_is_compatible(dev_ofnode(dev), 885 "st,stm32mp1-fmc2-nfc")) { 886 if (ebi_found) 887 cdev = pdev; 888 889 return cdev; 890 } 891 892 if (!ebi_found) 893 cdev = dev; 894 895 return cdev; 896} 897 898static int stm32_fmc2_nfc_probe(struct udevice *dev) 899{ 900 struct stm32_fmc2_nfc *nfc = dev_get_priv(dev); 901 struct stm32_fmc2_nand *nand = &nfc->nand; 902 struct nand_chip *chip = &nand->chip; 903 struct mtd_info *mtd = &chip->mtd; 904 struct nand_ecclayout *ecclayout; 905 struct udevice *cdev; 906 struct reset_ctl reset; 907 int oob_index, chip_cs, mem_region, ret; 908 unsigned int i; 909 int start_region = 0; 910 fdt_addr_t addr; 911 912 spin_lock_init(&nfc->controller.lock); 913 init_waitqueue_head(&nfc->controller.wq); 914 915 nfc->data = (void *)dev_get_driver_data(dev); 916 if (!nfc->data) 917 return -EINVAL; 918 919 if (nfc->data->get_cdev) { 920 cdev = nfc->data->get_cdev(dev); 921 if (!cdev) 922 return -EINVAL; 923 } else { 924 cdev = dev->parent; 925 } 926 927 ret = stm32_fmc2_nfc_parse_dt(dev, nfc); 928 if (ret) 929 return ret; 930 931 nfc->io_base = dev_read_addr(cdev); 932 if (nfc->io_base == FDT_ADDR_T_NONE) 933 return -EINVAL; 934 935 if (dev == cdev) 936 start_region = 1; 937 938 for (chip_cs = 0, mem_region = start_region; chip_cs < nfc->data->max_ncs; 939 chip_cs++, mem_region += 3) { 940 if (!(nfc->cs_assigned & BIT(chip_cs))) 941 continue; 942 943 addr = dev_read_addr_index(dev, mem_region); 944 if (addr == FDT_ADDR_T_NONE) { 945 dev_err(dev, "Resource data_base not found for cs%d", chip_cs); 946 return ret; 947 } 948 nfc->data_base[chip_cs] = addr; 949 950 addr = dev_read_addr_index(dev, mem_region + 1); 951 if (addr == FDT_ADDR_T_NONE) { 952 dev_err(dev, "Resource cmd_base not found for cs%d", chip_cs); 953 return ret; 954 } 955 nfc->cmd_base[chip_cs] = addr; 956 957 addr = dev_read_addr_index(dev, mem_region + 2); 958 if (addr == FDT_ADDR_T_NONE) { 959 dev_err(dev, "Resource addr_base not found for cs%d", chip_cs); 960 return ret; 961 } 962 nfc->addr_base[chip_cs] = addr; 963 } 964 965 /* Enable the clock */ 966 ret = clk_get_by_index(cdev, 0, &nfc->clk); 967 if (ret) 968 return ret; 969 970 ret = clk_enable(&nfc->clk); 971 if (ret) 972 return ret; 973 974 /* Reset */ 975 ret = reset_get_by_index(dev, 0, &reset); 976 if (!ret) { 977 reset_assert(&reset); 978 udelay(2); 979 reset_deassert(&reset); 980 } 981 982 stm32_fmc2_nfc_init(nfc, dev != cdev); 983 984 chip->controller = &nfc->base; 985 chip->select_chip = stm32_fmc2_nfc_select_chip; 986 chip->setup_data_interface = stm32_fmc2_nfc_setup_interface; 987 chip->cmd_ctrl = stm32_fmc2_nfc_cmd_ctrl; 988 chip->chip_delay = FMC2_RB_DELAY_US; 989 chip->options |= NAND_BUSWIDTH_AUTO | NAND_NO_SUBPAGE_WRITE | 990 NAND_USE_BOUNCE_BUFFER; 991 992 /* Default ECC settings */ 993 chip->ecc.mode = NAND_ECC_HW; 994 chip->ecc.size = FMC2_ECC_STEP_SIZE; 995 chip->ecc.strength = FMC2_ECC_BCH8; 996 997 /* Disable Write Protect */ 998 if (dm_gpio_is_valid(&nand->wp_gpio)) 999 dm_gpio_set_value(&nand->wp_gpio, 0); 1000 1001 ret = nand_scan_ident(mtd, nand->ncs, NULL); 1002 if (ret) 1003 return ret; 1004 1005 /* 1006 * Only NAND_ECC_HW mode is actually supported 1007 * Hamming => ecc.strength = 1 1008 * BCH4 => ecc.strength = 4 1009 * BCH8 => ecc.strength = 8 1010 * ECC sector size = 512 1011 */ 1012 if (chip->ecc.mode != NAND_ECC_HW) { 1013 dev_err(dev, "Nand_ecc_mode is not well defined in the DT\n"); 1014 return -EINVAL; 1015 } 1016 1017 ret = nand_check_ecc_caps(chip, &stm32_fmc2_nfc_ecc_caps, 1018 mtd->oobsize - FMC2_BBM_LEN); 1019 if (ret) { 1020 dev_err(dev, "No valid ECC settings set\n"); 1021 return ret; 1022 } 1023 1024 if (chip->bbt_options & NAND_BBT_USE_FLASH) 1025 chip->bbt_options |= NAND_BBT_NO_OOB; 1026 1027 stm32_fmc2_nfc_nand_callbacks_setup(chip); 1028 1029 /* Define ECC layout */ 1030 ecclayout = &nfc->ecclayout; 1031 ecclayout->eccbytes = chip->ecc.bytes * 1032 (mtd->writesize / chip->ecc.size); 1033 oob_index = FMC2_BBM_LEN; 1034 for (i = 0; i < ecclayout->eccbytes; i++, oob_index++) 1035 ecclayout->eccpos[i] = oob_index; 1036 ecclayout->oobfree->offset = oob_index; 1037 ecclayout->oobfree->length = mtd->oobsize - ecclayout->oobfree->offset; 1038 chip->ecc.layout = ecclayout; 1039 1040 if (chip->options & NAND_BUSWIDTH_16) 1041 stm32_fmc2_nfc_set_buswidth_16(nfc, true); 1042 1043 ret = nand_scan_tail(mtd); 1044 if (ret) 1045 return ret; 1046 1047 return nand_register(0, mtd); 1048} 1049 1050static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp1_data = { 1051 .max_ncs = 2, 1052 .get_cdev = stm32_fmc2_nfc_get_cdev, 1053}; 1054 1055static const struct stm32_fmc2_nfc_data stm32_fmc2_nfc_mp25_data = { 1056 .max_ncs = 4, 1057}; 1058 1059static const struct udevice_id stm32_fmc2_nfc_match[] = { 1060 { 1061 .compatible = "st,stm32mp15-fmc2", 1062 .data = (ulong)&stm32_fmc2_nfc_mp1_data, 1063 }, 1064 { 1065 .compatible = "st,stm32mp1-fmc2-nfc", 1066 .data = (ulong)&stm32_fmc2_nfc_mp1_data, 1067 }, 1068 { 1069 .compatible = "st,stm32mp25-fmc2-nfc", 1070 .data = (ulong)&stm32_fmc2_nfc_mp25_data, 1071 }, 1072 { /* Sentinel */ } 1073}; 1074 1075U_BOOT_DRIVER(stm32_fmc2_nfc) = { 1076 .name = "stm32_fmc2_nfc", 1077 .id = UCLASS_MTD, 1078 .of_match = stm32_fmc2_nfc_match, 1079 .probe = stm32_fmc2_nfc_probe, 1080 .priv_auto = sizeof(struct stm32_fmc2_nfc), 1081}; 1082 1083void board_nand_init(void) 1084{ 1085 struct udevice *dev; 1086 int ret; 1087 1088 ret = uclass_get_device_by_driver(UCLASS_MTD, 1089 DM_DRIVER_GET(stm32_fmc2_nfc), 1090 &dev); 1091 if (ret && ret != -ENODEV) 1092 log_err("Failed to initialize STM32 FMC2 NFC controller. (error %d)\n", 1093 ret); 1094} 1095