Searched refs:effective_cs (Results 1 - 11 of 11) sorted by relevance
/u-boot/drivers/ddr/marvell/a38x/ |
H A D | ddr3_training_leveling.h | 12 int ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs,
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H A D | ddr3_training_leveling.c | 53 for (effective_cs = 0; effective_cs < MAX_CS_NUM; effective_cs++) 56 rl_values[effective_cs][bus_num][if_id] = 0; 58 for (effective_cs = 0; effective_cs < max_cs; effective_cs++) { 94 effective_cs, STRESS_NONE, DURATION_SINGLE)); 115 (0x301b01 | effective_cs << 2), 0x3c3fef)); 214 if_id, effective_cs, bus_nu 764 ddr3_tip_calc_cs_mask(u32 dev_num, u32 if_id, u32 effective_cs, u32 *cs_mask) argument [all...] |
H A D | ddr3_training_pbs.c | 73 CRX_PHY_REG(effective_cs) : 74 CTX_PHY_REG(effective_cs); 187 (0x54 + effective_cs * 0x10) : 188 (0x14 + effective_cs * 0x10); 194 (0x55 + effective_cs * 0x10) : 195 (0x15 + effective_cs * 0x10); 247 (0x54 + effective_cs * 0x10) : 248 (0x14 + effective_cs * 0x10); 257 (0x55 + effective_cs * 0x10) : 258 (0x15 + effective_cs * [all...] |
H A D | ddr3_training.c | 64 u32 effective_cs = 0; variable 1271 ddr3_tip_calc_cs_mask(dev_num, if_id, effective_cs, 1903 if (cs_bitmask != effective_cs) { 1909 (effective_cs * 0x4), 2014 WL_PHY_REG(effective_cs), 2019 RL_PHY_REG(effective_cs), 2024 CRX_PHY_REG(effective_cs), phy_reg3_val)); 2028 CTX_PHY_REG(effective_cs), phy_reg1_val)); 2032 PBS_TX_BCAST_PHY_REG(effective_cs), 0x0)); 2036 PBS_RX_BCAST_PHY_REG(effective_cs), [all...] |
H A D | ddr3_training_centralization.c | 99 reg_phy_off = CTX_PHY_REG(effective_cs); 103 reg_phy_off = CRX_PHY_REG(effective_cs); 221 effective_cs, pattern_id, 474 effective_cs, ®); 488 effective_cs, reg)); 544 if ((ddr3_tip_special_rx_run_once_flag & (1 << effective_cs)) == (1 << effective_cs)) 547 ddr3_tip_special_rx_run_once_flag |= (1 << effective_cs); 659 PBS_RX_PHY_REG(effective_cs, pad_num), 669 PBS_RX_PHY_REG(effective_cs, pad_nu [all...] |
H A D | mv_ddr4_training_calibration.c | 306 0x10 + pad_num + effective_cs * 0x10, 314 CTX_PHY_REG(effective_cs), 1035 DDR_PHY_DATA, RESULT_PHY_REG + effective_cs + 4 * (1 - mode), 1041 dmin_phy_reg_table[effective_cs * 5 + subphy_num][0], DDR_PHY_CONTROL, 1042 dmin_phy_reg_table[effective_cs * 5 + subphy_num][1], ®_val); 1050 dmin_phy_reg_table[effective_cs * 5 + subphy_num][0], DDR_PHY_CONTROL, 1051 dmin_phy_reg_table[effective_cs * 5 + subphy_num][1], reg_val); 1143 reg_addr = PBS_RX_BCAST_PHY_REG(effective_cs); 1145 reg_addr = PBS_TX_BCAST_PHY_REG(effective_cs); 1150 reg_addr = PBS_RX_PHY_REG(effective_cs, DQSP_PA [all...] |
H A D | mv_ddr4_training_leveling.c | 61 effective_cs << ODPG_DATA_CS_OFFS, 88 effective_cs << ODPG_DATA_CS_OFFS, 143 effective_cs << ODPG_DATA_CS_OFFS, 164 effective_cs << ODPG_DATA_CS_OFFS, 180 ((SDRAM_CS_SIZE + 1) * effective_cs)), 1, read_pattern); 346 WL_PHY_REG(effective_cs), &rd_data); 366 WL_PHY_REG(effective_cs), wr_data); 373 WL_PHY_REG(effective_cs), wr_data); 381 WL_PHY_REG(effective_cs), wr_data);
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H A D | mv_ddr4_training.c | 500 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("RECEIVER_CALIBRATION_MASK_BIT #%d\n", effective_cs)); 513 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("WL_PHASE_CORRECTION_MASK_BIT #%d\n", effective_cs)); 526 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DQ_VREF_CALIBRATION_MASK_BIT #%d\n", effective_cs)); 539 DEBUG_TRAINING_IP(DEBUG_LEVEL_INFO, ("DM_TUNING_MASK_BIT #%d\n", effective_cs)); 540 status = mv_ddr4_dm_tuning(effective_cs, pbs_tap_factor);
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H A D | ddr3_training_ip_engine.c | 522 (0x3 | (effective_cs << 26)), 0xc000003)); 546 delay_between_burst, rd_mode, effective_cs, STRESS_NONE, 598 reg_data = PBS_RX_BCAST_PHY_REG(effective_cs); 601 reg_data = PBS_TX_BCAST_PHY_REG(effective_cs); 612 reg_data = CTX_PHY_REG(effective_cs); 616 reg_data = CRX_PHY_REG(effective_cs); 1038 (effective_cs << 26); 1045 ODPG_DATA_CTRL_REG, (0x1 | (effective_cs << 26)), 1621 CTX_PHY_REG(effective_cs), 1628 RL_PHY_REG(effective_cs), [all...] |
H A D | ddr3_init.h | 122 extern u32 effective_cs;
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H A D | mv_ddr4_mpr_pda_if.c | 454 if (effective_cs == 0) 551 if (effective_cs == 0)
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