| /u-boot/board/ti/ks2_evm/ |
| H A D | ddr3_cfg.c | 31 .dtcr = 0x710035C7ul,
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| H A D | ddr3_k2g.c | 33 .dtcr = 0x710035C7ul,
73 .dtcr = 0x710035C7ul,
134 .dtcr = 0x710035C7ul,
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| /u-boot/arch/arm/mach-keystone/include/mach/ |
| H A D | ddr3.h | 31 unsigned int dtcr; member in struct:ddr3_phy_config
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| /u-boot/arch/arm/mach-sunxi/ |
| H A D | dram_sun8i_a33.c | 186 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
188 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
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| H A D | dram_sun50i_h6.c | 450 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
452 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
455 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
466 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
468 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
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| H A D | dram_sun8i_a83t.c | 218 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x3 << 24);
220 clrsetbits_le32(&mctl_ctl->dtcr, 0x3 << 24, 0x1 << 24);
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| H A D | dram_sunxi_dw.c | 564 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
601 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
711 clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
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| H A D | dram_sun8i_a23.c | 139 writel(0x01000081, &mctl_phy->dtcr);
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| H A D | dram_sun9i.c | 690 &mctl_phy->dtcr);
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| /u-boot/arch/arm/include/asm/arch-sunxi/ |
| H A D | dram_sun8i_a23.h | 189 u32 dtcr; /* 0x68 */ member in struct:sunxi_mctl_phy_reg
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| H A D | dram_sun50i_h6.h | 201 u32 dtcr[2]; /* 0x200 */ member in struct:sunxi_mctl_phy_reg
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| H A D | dram_sun9i.h | 116 u32 dtcr; /* 0xb0 data training configuration register */ member in struct:sunxi_mctl_phy_reg
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| H A D | dram_sun8i_a83t.h | 107 u32 dtcr; /* 0xc0 */ member in struct:sunxi_mctl_ctl_reg
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| H A D | dram_sun8i_a33.h | 107 u32 dtcr; /* 0xc0 */ member in struct:sunxi_mctl_ctl_reg
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| H A D | dram_sunxi_dw.h | 104 u32 dtcr; /* 0xc0 */ member in struct:sunxi_mctl_ctl_reg
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| /u-boot/arch/arm/mach-keystone/ |
| H A D | ddr3_spd.c | 38 debug_ddr_cfg("dtcr 0x%08X\n", ptr->dtcr);
359 spd_cb->phy_cfg.dtcr = (spd->rank == 2) ? 0x730035C7 : 0x710035C7;
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| H A D | ddr3.c | 58 __raw_writel(phy_cfg->dtcr, base + KS2_DDRPHY_DTCR_OFFSET);
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| /u-boot/arch/powerpc/include/asm/ |
| H A D | immap_83xx.h | 398 u32 dtcr; member in struct:ios83xx
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