/u-boot/arch/mips/mach-bmips/ |
H A D | Makefile | 3 obj-y += dram.o
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/u-boot/arch/arm/mach-mvebu/armada8k/ |
H A D | Makefile | 5 obj-y = cpu.o cache_llc.o dram.o
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/u-boot/arch/riscv/cpu/generic/ |
H A D | Makefile | 5 obj-y += dram.o
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/u-boot/arch/arm/mach-lpc32xx/ |
H A D | dram.c | 3 * LPC32xx dram init 25 void ddr_init(struct emc_dram_settings *dram) argument 37 writel(dram->cmddelay, &clk->sdramclk_ctrl); 38 writel(dram->config0, &emc->config0); 39 writel(dram->rascas0, &emc->rascas0); 40 writel(dram->rdconfig, &emc->read_config); 42 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); 43 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); 44 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); 45 writel((ck / dram [all...] |
H A D | Makefile | 8 obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
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/u-boot/arch/riscv/cpu/fu540/ |
H A D | Makefile | 9 obj-y += dram.o
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/u-boot/arch/riscv/cpu/fu740/ |
H A D | Makefile | 9 obj-y += dram.o
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/u-boot/arch/riscv/cpu/jh7110/ |
H A D | Makefile | 9 obj-y += dram.o
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/u-boot/arch/riscv/cpu/cv1800b/ |
H A D | Makefile | 5 obj-y += dram.o
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/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun4i.c | 7 * Based on sun4i Linux kernel sources mach-sunxi/pm/standby/dram*.c 26 #include <asm/arch/dram.h> 61 struct sunxi_dram_reg *dram = local 74 setbits_le32(&dram->mcr, DRAM_MCR_RESET); 76 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); 80 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); 82 setbits_le32(&dram->mcr, DRAM_MCR_RESET); 101 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 104 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), 106 clrsetbits_le32(&dram 114 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 121 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 136 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 153 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 166 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 231 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 368 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 387 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 408 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 432 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 470 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 483 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 503 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 513 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local 564 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; local [all...] |
/u-boot/drivers/ram/rockchip/ |
H A D | sdram_px30.c | 142 static void rkclk_ddr_reset(struct dram_info *dram, argument 148 &dram->cru->softrst_con[1]); 150 &dram->cru->softrst_con[2]); 153 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) argument 181 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); 183 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); 185 &dram->cru->pll[1].con1); 189 if (LOCK(readl(&dram->cru->pll[1].con1))) 194 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); 197 static void rkclk_configure_ddr(struct dram_info *dram, argument 246 set_ctl_address_map(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 305 read_mr(struct dram_info *dram, u32 rank, u32 mr_num) argument 316 check_rd_gate(struct dram_info *dram) argument 351 data_training(struct dram_info *dram, u32 cs, u32 dramtype) argument 374 dram_set_bw(struct dram_info *dram, u32 bw) argument 379 set_ddrconfig(struct dram_info *dram, u32 ddrconfig) argument 416 dram_all_config(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 432 enable_low_power(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument 484 sdram_init_(struct dram_info *dram, struct px30_sdram_params *sdram_params, u32 pre_init) argument 565 dram_detect_cap(struct dram_info *dram, struct px30_sdram_params *sdram_params, unsigned char channel) argument 646 sdram_init_detect(struct dram_info *dram, struct px30_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rk3328.c | 66 static void rkclk_ddr_reset(struct dram_info *dram, argument 72 &dram->cru->softrst_con[5]); 73 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]); 76 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) argument 104 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con); 105 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); 107 &dram->cru->dpll_con[1]); 111 if (LOCK(readl(&dram->cru->dpll_con[1]))) 116 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con); 119 static void rkclk_configure_ddr(struct dram_info *dram, argument 217 set_ctl_address_map(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 234 data_training(struct dram_info *dram, u32 cs, u32 dramtype) argument 257 rx_deskew_switch_adjust(struct dram_info *dram) argument 273 tx_deskew_switch_adjust(struct dram_info *dram) argument 280 set_ddrconfig(struct dram_info *dram, u32 ddrconfig) argument 304 dram_all_config(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 320 enable_low_power(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument 342 sdram_init(struct dram_info *dram, struct rk3328_sdram_params *sdram_params, u32 pre_init) argument 398 dram_detect_cap(struct dram_info *dram, struct rk3328_sdram_params *sdram_params, unsigned char channel) argument 471 sdram_init_detect(struct dram_info *dram, struct rk3328_sdram_params *sdram_params) argument [all...] |
H A D | sdram_rv1126.c | 287 static void rkclk_ddr_reset(struct dram_info *dram, argument 296 &dram->cru->softrst_con[12]); 299 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) argument 335 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); 337 writel(0x1f000000, &dram->cru->clksel_con[64]); 338 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); 342 clrsetbits_le32(&dram->cru->pll[1].con2, 350 &dram->cru->pll[1].con3); 353 &dram->cru->pll[1].con1); 357 if (LOCK(readl(&dram 365 rkclk_configure_ddr(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 477 sw_set_req(struct dram_info *dram) argument 485 sw_set_ack(struct dram_info *dram) argument 499 set_ctl_address_map(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 540 phy_pll_set(struct dram_info *dram, u32 freq, u32 wait) argument 779 set_lp4_vref(struct dram_info *dram, struct lp4_info *lp4_info, u32 freq_mhz, u32 dst_fsp, u32 dramtype) argument 850 set_ds_odt(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 dst_fsp) argument 1191 sdram_cmd_dq_path_remap(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 1211 phy_cfg(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 1257 update_refresh_reg(struct dram_info *dram) argument 1272 read_mr(struct dram_info *dram, u32 rank, u32 mr_num, u32 dramtype) argument 1309 send_a_refresh(struct dram_info *dram) argument 1318 enter_sr(struct dram_info *dram, u32 en) argument 1341 record_dq_prebit(struct dram_info *dram) argument 1365 update_dq_rx_prebit(struct dram_info *dram) argument 1375 update_dq_tx_prebit(struct dram_info *dram) argument 1386 update_ca_prebit(struct dram_info *dram) argument 1402 modify_ca_deskew(struct dram_info *dram, u32 dir, int delta_dif, int delta_sig, u32 cs, u32 dramtype) argument 1452 get_min_value(struct dram_info *dram, u32 signal, u32 rank) argument 1481 low_power_update(struct dram_info *dram, u32 en) argument 1503 modify_dq_deskew(struct dram_info *dram, u32 signal, u32 dir, int delta_dif, int delta_sig, u32 rank) argument 1543 data_training_rg(struct dram_info *dram, u32 cs, u32 dramtype) argument 1593 data_training_wl(struct dram_info *dram, u32 cs, u32 dramtype, u32 rank) argument 1663 data_training_rd(struct dram_info *dram, u32 cs, u32 dramtype, u32 mhz) argument 1780 data_training_wr(struct dram_info *dram, u32 cs, u32 dramtype, u32 mhz, u32 dst_fsp) argument 1893 data_training(struct dram_info *dram, u32 cs, struct rv1126_sdram_params *sdram_params, u32 dst_fsp, u32 training_flag) argument 1938 get_wrlvl_val(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2052 high_freq_training(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 fsp) argument 2165 set_ddrconfig(struct dram_info *dram, u32 ddrconfig) argument 2171 update_noc_timing(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2213 split_setup(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2259 split_bypass(struct dram_info *dram) argument 2273 dram_all_config(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2306 enable_low_power(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2352 sdram_init_(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 post_init) argument 2469 dram_detect_cap(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, unsigned char channel) argument 2618 dram_detect_cs1_row(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, unsigned char channel) argument 2687 sdram_init_detect(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument 2802 pre_set_rate(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 dst_fsp, u32 dst_fsp_lp4) argument 2928 save_fsp_param(struct dram_info *dram, u32 dst_fsp, struct rv1126_sdram_params *sdram_params) argument 3167 ddr_set_rate(struct dram_info *dram, struct rv1126_sdram_params *sdram_params, u32 freq, u32 cur_freq, u32 dst_fsp, u32 dst_fsp_lp4, u32 training_en) argument 3350 ddr_set_rate_for_fsp(struct dram_info *dram, struct rv1126_sdram_params *sdram_params) argument [all...] |
/u-boot/arch/arm/include/asm/arch-lpc32xx/ |
H A D | sys_proto.h | 20 void ddr_init(const struct emc_dram_settings *dram);
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/u-boot/arch/arm/mach-uniphier/clk/ |
H A D | Makefile | 5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o 6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o 7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o 8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o 9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o 10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
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/u-boot/arch/x86/cpu/qemu/ |
H A D | Makefile | 8 obj-y += dram.o
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/u-boot/arch/x86/cpu/quark/ |
H A D | Makefile | 5 obj-y += car.o dram.o msg_port.o quark.o
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/u-boot/arch/mips/mach-ath79/ |
H A D | Makefile | 5 obj-y += dram.o
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/u-boot/arch/mips/mach-mtmips/mt7620/ |
H A D | Makefile | 5 obj-y += dram.o
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/u-boot/arch/mips/mach-mtmips/mt7621/spl/ |
H A D | Makefile | 6 obj-y += dram.o
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/u-boot/arch/arm/mach-orion5x/ |
H A D | Makefile | 11 obj-y += dram.o
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/u-boot/arch/mips/mach-mscc/ |
H A D | Makefile | 5 obj-y += cpu.o dram.o reset.o phy.o lowlevel_init.o
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/u-boot/drivers/mmc/ |
H A D | mv_sdhci.c | 27 const struct mbus_dram_target_info *dram; local 30 dram = mvebu_mbus_dram_info(); 37 for (i = 0; i < dram->num_cs; i++) { 38 const struct mbus_dram_window *cs = dram->cs + i; 42 (dram->mbus_dram_target_id << 4) | 1,
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/u-boot/board/sunxi/ |
H A D | dram_sun5i_auto.c | 1 /* DRAM parameters for auto dram configuration on sun5i and sun7i */ 5 #include <asm/arch/dram.h>
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H A D | dram_sun4i_auto.c | 3 #include <asm/arch/dram.h>
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