Searched refs:dqx_ctl (Results 1 - 4 of 4) sorted by relevance

/u-boot/arch/mips/mach-octeon/include/mach/
H A Docteon_ddr.h376 u8 odt_ena; /* FIX: dqx_ctl for Octeon 3 DDR4 */
417 * .dqx_ctl: Drive strength control for DDR_DQX/DDR_DQS_X_P/N drivers.
525 u8 dqx_ctl; member in struct:ddr3_custom_config
H A Dcvmx-lmcx-defs.h337 uint64_t dqx_ctl:4; member in struct:cvmx_lmcx_comp_ctl2::cvmx_lmcx_comp_ctl2_s
350 uint64_t dqx_ctl:4; member in struct:cvmx_lmcx_comp_ctl2::cvmx_lmcx_comp_ctl2_cn61xx
372 uint64_t dqx_ctl:4; member in struct:cvmx_lmcx_comp_ctl2::cvmx_lmcx_comp_ctl2_cn70xx
/u-boot/drivers/ram/octeon/
H A Docteon_ddr.c986 comp_ctl2.cn78xx.dqx_ctl =
987 (custom_lmc_config->dqx_ctl ==
988 0) ? 4 : custom_lmc_config->dqx_ctl;
1027 comp_ctl2.cn78xx.dqx_ctl =
H A Docteon3_lmc.c1841 static int compute_vref_1slot_2rank(int rtt_wr, int rtt_park, int dqx_ctl, argument
1854 u64 dqx_ctl_s = (dqx_ctl == 0 ? 1 * 1024 * 1024 : dqx_ctl);
1880 debug("rtt_wr: %d, rtt_park: %d, dqx_ctl: %d, rank_count: %d\n",
1881 rtt_wr, rtt_park, dqx_ctl, rank_count);
1892 int dqx_ctl, int rtt_nom,
1904 u64 dqx_ctl_s = (dqx_ctl == 0 ? 1 * 1024 * 1024 : dqx_ctl);
1947 debug("rtt_wr:%d, rtt_park_00:%d, rtt_park_01:%d, dqx_ctl:%d, rtt_nom:%d, vref_value:%d (0x%x)\n",
1948 rtt_wr, rtt_park_00, rtt_park_01, dqx_ctl, rtt_no
1890 compute_vref_2slot_2rank(int rtt_wr, int rtt_park_00, int rtt_park_01, int dqx_ctl, int rtt_nom, int dram_connection) argument
1963 int rtt_wr, dqx_ctl, rtt_nom, index; local
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