Searched refs:div_factor (Results 1 - 5 of 5) sorted by relevance

/u-boot/drivers/video/
H A Dssd2828.c254 u32 div_factor = 1, mul_factor, fr = 0; local
258 while (reference_freq_khz / (div_factor + 1) >= 5000)
259 div_factor++;
260 if (div_factor > 31)
261 div_factor = 31;
263 mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
266 output_freq_kbps = reference_freq_khz * mul_factor / div_factor;
275 return (fr << 14) | (div_factor << 8) | mul_factor;
281 u32 div_factor = (pll_config >> 8) & 0x1F; local
284 if (div_factor
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/u-boot/drivers/video/bridge/
H A Dssd2825.c288 u32 div_factor = 1, mul_factor, fr = 0; local
290 while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK)
291 div_factor++;
292 if (div_factor > 31)
293 div_factor = 31;
295 mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor,
298 priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor;
307 return (fr << 14) | (div_factor << 8) | mul_factor;
/u-boot/drivers/clk/
H A Dclk-hsdk-cgu.c566 u32 div_factor = hsdk_idiv_read(clk); local
568 div_factor &= CGU_IDIV_MASK;
570 pr_debug("current configurarion: %#x (%d)\n", div_factor, div_factor);
572 if (div_factor == 0)
575 return parent_rate / div_factor;
656 u32 div_factor; local
658 div_factor = parent_rate / rate;
659 if (abs(rate - parent_rate / (div_factor + 1)) <=
660 abs(rate - parent_rate / div_factor)) {
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/u-boot/drivers/i2c/
H A Dmeson_i2c.c49 unsigned char div_factor; member in struct:meson_i2c_data
241 div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor);
287 .div_factor = 4,
291 .div_factor = 4,
295 .div_factor = 3,
/u-boot/arch/arm/mach-omap2/omap5/
H A Dhwinit.c201 u32 srcomp_value, mul_factor, div_factor, clk_val, i; local
209 div_factor = srcomp_parameters[sysclk_ind].divide_factor;
216 (div_factor << DIVIDE_FACTOR_XS_SHIFT);
248 (div_factor << DIVIDE_FACTOR_XS_SHIFT);

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