/u-boot/drivers/mtd/nvmxip/ |
H A D | nvmxip_qspi.c | 41 ret = dev_read_u32(dev, "lba_shift", &plat->lba_shift); 47 ret = dev_read_u32(dev, "lba", (u32 *)&plat->lba);
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/u-boot/drivers/sysreset/ |
H A D | sysreset_syscon.c | 55 err = dev_read_u32(dev, "offset", &priv->offset); 61 mask_err = dev_read_u32(dev, "mask", &priv->mask); 62 value_err = dev_read_u32(dev, "value", &priv->value);
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/u-boot/drivers/power/regulator/ |
H A D | anatop_regulator.c | 190 ret = dev_read_u32(dev, 196 ret = dev_read_u32(dev, 202 ret = dev_read_u32(dev, 208 ret = dev_read_u32(dev, 214 ret = dev_read_u32(dev, 220 ret = dev_read_u32(dev, 227 dev_read_u32(dev, "anatop-delay-reg-offset", 229 dev_read_u32(dev, "anatop-delay-bit-width", 231 dev_read_u32(dev, "anatop-delay-bit-shift",
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/u-boot/drivers/i2c/ |
H A D | acpi_i2c.c | 192 dev_read_u32(dev, "acpi,uid", &priv->uid); 194 dev_read_u32(dev, "acpi,wake", &priv->wake); 199 dev_read_u32(dev, "hid-descr-addr", &priv->hid_desc_reg_offset); 200 dev_read_u32(dev, "reset-delay-ms", &priv->reset_delay_ms); 201 dev_read_u32(dev, "reset-off-delay-ms", &priv->reset_off_delay_ms); 202 dev_read_u32(dev, "enable-delay-ms", &priv->enable_delay_ms); 203 dev_read_u32(dev, "enable-off-delay-ms", &priv->enable_off_delay_ms); 204 dev_read_u32(dev, "stop-delay-ms", &priv->stop_delay_ms); 205 dev_read_u32(dev, "stop-off-delay-ms", &priv->stop_off_delay_ms);
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/u-boot/drivers/cpu/ |
H A D | cpu_sandbox.c | 70 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); 73 ret = dev_read_u32(dev->parent, "timebase-frequency",
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H A D | riscv_cpu.c | 52 dev_read_u32(dev, "clock-frequency", (u32 *)&info->cpu_freq); 59 ret = dev_read_u32(dev, "i-cache-size", &i_cache_size); 62 ret = dev_read_u32(dev, "d-cache-size", &d_cache_size); 117 ret = dev_read_u32(dev, "timebase-frequency", &plat->timebase_freq); 120 dev_read_u32(dev->parent, "timebase-frequency",
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/u-boot/drivers/cache/ |
H A D | cache-l2x0.c | 22 if (!dev_read_u32(dev, "prefetch-data", &prefetch)) { 29 if (!dev_read_u32(dev, "prefetch-instr", &prefetch)) {
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/u-boot/boot/ |
H A D | vbe_simple.c | 190 if (dev_read_u32(dev, "area-start", &priv->area_start) || 191 dev_read_u32(dev, "area-size", &priv->area_size) || 192 dev_read_u32(dev, "version-offset", &priv->version_offset) || 193 dev_read_u32(dev, "version-size", &priv->version_size) || 194 dev_read_u32(dev, "state-offset", &priv->state_offset) || 195 dev_read_u32(dev, "state-size", &priv->state_size)) 197 dev_read_u32(dev, "skip-offset", &priv->skip_offset);
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/u-boot/drivers/misc/ |
H A D | microchip_flexcom.c | 33 ret = dev_read_u32(dev, "atmel,flexcom-mode", &plat->flexcom_mode);
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H A D | usb251xb.c | 449 if (!dev_read_u32(dev, "oc-delay-us", &property_u32)) { 495 if (!dev_read_u32(dev, "sp-max-total-current-microamp", &property_u32)) 499 if (!dev_read_u32(dev, "bp-max-total-current-microamp", &property_u32)) 503 if (!dev_read_u32(dev, "sp-max-removable-current-microamp", 508 if (!dev_read_u32(dev, "bp-max-removable-current-microamp", 513 if (!dev_read_u32(dev, "power-on-time-ms", &property_u32))
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/u-boot/drivers/pinctrl/tegra/ |
H A D | pinctrl-tegra20.c | 20 ret = dev_read_u32(config, "nvidia,pull", &pull); 24 ret = dev_read_u32(config, "nvidia,tristate", &tristate);
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/u-boot/drivers/firmware/scmi/ |
H A D | smccc_agent.c | 69 if (dev_read_u32(dev, "arm,smc-id", &func_id)) { 92 if (dev_read_u32(protocol, "arm,smc-id", &func_id)) {
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/u-boot/drivers/power/acpi_pmc/ |
H A D | acpi-pmc-uclass.c | 214 ret = dev_read_u32(dev, "gpe0-dwx-mask", &upriv->gpe0_dwx_mask); 217 ret = dev_read_u32(dev, "gpe0-dwx-shift-base", 221 ret = dev_read_u32(dev, "gpe0-sts", &upriv->gpe0_sts_reg); 225 ret = dev_read_u32(dev, "gpe0-en", &upriv->gpe0_en_reg);
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/u-boot/drivers/net/ |
H A D | sandbox-raw-bus.c | 28 dev_read_u32(dev, "skip-localhost", &skip_localhost);
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/u-boot/drivers/ram/k3-ddrss/ |
H A D | k3-ddrss.c | 380 ret = dev_read_u32(dev, "instance", &ddrss->instance); 389 ret = dev_read_u32(dev, "ti,ddr-freq0", &ddrss->ddr_freq0); 396 ret = dev_read_u32(dev, "ti,ddr-freq1", &ddrss->ddr_freq1); 400 ret = dev_read_u32(dev, "ti,ddr-freq2", &ddrss->ddr_freq2); 404 ret = dev_read_u32(dev, "ti,ddr-fhs-cnt", &ddrss->ddr_fhs_cnt); 751 ret = dev_read_u32(dev, "intrlv-gran", &msmc->gran); 758 ret = dev_read_u32(dev, "intrlv-size", &msmc->size); 765 ret = dev_read_u32(dev, "ecc-enable", &msmc->enable); 772 ret = dev_read_u32(dev, "emif-config", &msmc->config); 779 ret = dev_read_u32(de [all...] |
/u-boot/drivers/mmc/ |
H A D | ca_dw_mmc.c | 107 dev_read_u32(dev, "sd_dll_ctrl", &tmp); 112 dev_read_u32(dev, "io_drv_ctrl", &tmp);
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H A D | snps_dw_mmc.c | 88 ret = dev_read_u32(dev, "fifo-depth", &fifo_depth); 106 ret = dev_read_u32(dev, "max-frequency", &priv->f_max);
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H A D | am654_sdhci.c | 600 ret = dev_read_u32(dev, "ti,otap-del-sel-legacy", 609 ret = dev_read_u32(dev, td[i].otap_binding, 621 ret = dev_read_u32(dev, td[i].itap_binding, 699 ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp); 703 ret = dev_read_u32(dev, "ti,driver-strength-ohm", 730 dev_read_u32(dev, "ti,strobe-sel", &plat->strb_sel); 731 dev_read_u32(dev, "ti,clkbuf-sel", &plat->clkbuf_sel);
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/u-boot/drivers/bootcount/ |
H A D | bootcount_dm_i2c.c | 72 ret = dev_read_u32(dev, "offset", &priv->offset);
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/u-boot/drivers/button/ |
H A D | button-gpio.c | 58 ret = dev_read_u32(dev, "linux,code", &priv->linux_code);
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/u-boot/arch/x86/cpu/intel_common/ |
H A D | generic_wifi.c | 95 ret = dev_read_u32(dev, "acpi,wake", &config.wake);
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/u-boot/test/dm/ |
H A D | mux-emul.c | 39 ret = dev_read_u32(dev, "idle-state", &idle_state);
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/u-boot/drivers/pinctrl/nxp/ |
H A D | pinctrl-mxs.c | 32 ret = dev_read_u32(conf, "fsl,drive-strength", &val); 36 ret = dev_read_u32(conf, "fsl,voltage", &val); 40 ret = dev_read_u32(conf, "fsl,pull-up", &val);
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/u-boot/drivers/usb/mtu3/ |
H A D | mtu3_host.c | 117 dev_read_u32(dev, "mediatek,u3p-dis-msk", &u3h->u3p_dis_msk);
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/u-boot/drivers/gpio/ |
H A D | mt7620_gpio.c | 117 ret = dev_read_u32(dev, "mediatek,gpio-num", &priv->count);
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