| /u-boot/board/variscite/imx8mn_var_som/ |
| H A D | ddr4_timing.c | 268 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
512 .fsp_cfg = ddr_fsp0_2d_cfg,
513 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/freescale/imx8mn_evk/ |
| H A D | ddr4_timing_ld.c | 796 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1038 .fsp_cfg = ddr_fsp0_2d_cfg,
1039 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | ddr4_timing.c | 792 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1036 .fsp_cfg = ddr_fsp0_2d_cfg,
1037 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | lpddr4_timing.c | 907 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1569 .fsp_cfg = ddr_fsp0_2d_cfg,
1570 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | lpddr4_timing_ld.c | 793 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1422 .fsp_cfg = ddr_fsp0_2d_cfg,
1423 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/toradex/verdin-imx8mp/ |
| H A D | lpddr4_timing.c | 1210 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1860 .fsp_cfg = ddr_fsp0_2d_cfg,
1861 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
1909 apply_cfg_patch(ddr_fsp0_2d_cfg, ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/google/imx8mq_phanbell/ |
| H A D | lpddr4_timing_1g.c | 1071 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1713 .fsp_cfg = ddr_fsp0_2d_cfg,
1714 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/beacon/imx8mn/ |
| H A D | lpddr4_2g_timing.c | 792 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1422 .fsp_cfg = ddr_fsp0_2d_cfg,
1423 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | lpddr4_timing.c | 789 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1415 .fsp_cfg = ddr_fsp0_2d_cfg,
1416 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/freescale/imx8mm_evk/ |
| H A D | lpddr4_timing.c | 1169 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1830 .fsp_cfg = ddr_fsp0_2d_cfg,
1831 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/kontron/pitx_imx8m/ |
| H A D | lpddr4_timing_2gb.c | 1172 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1834 .fsp_cfg = ddr_fsp0_2d_cfg,
1835 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | lpddr4_timing_4gb.c | 1172 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1834 .fsp_cfg = ddr_fsp0_2d_cfg,
1835 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/advantech/imx8mp_rsb3720a1/ |
| H A D | lpddr4_timing_rsb3720a1_4G.c | 1170 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1829 .fsp_cfg = ddr_fsp0_2d_cfg,
1830 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | lpddr4_timing_rsb3720a1_6G.c | 1183 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1842 .fsp_cfg = ddr_fsp0_2d_cfg,
1843 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/data_modul/imx8mm_edm_sbc/ |
| H A D | lpddr4_timing_2G_32.c | 1167 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1828 .fsp_cfg = ddr_fsp0_2d_cfg,
1829 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| H A D | lpddr4_timing_4G_32.c | 1167 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1828 .fsp_cfg = ddr_fsp0_2d_cfg,
1829 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/engicam/imx8mp/ |
| H A D | lpddr4_timing.c | 1181 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1832 .fsp_cfg = ddr_fsp0_2d_cfg,
1833 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/msc/sm2s_imx8mp/ |
| H A D | lpddr4_timing.c | 1174 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1824 .fsp_cfg = ddr_fsp0_2d_cfg,
1825 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/cloos/imx8mm_phg/ |
| H A D | lpddr4_timing.c | 1167 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1828 .fsp_cfg = ddr_fsp0_2d_cfg,
1829 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/freescale/imx93_evk/ |
| H A D | lpddr4x_timing_ld.c | 887 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1478 .fsp_cfg = ddr_fsp0_2d_cfg,
1479 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/phytec/phycore_imx8mm/ |
| H A D | lpddr4_timing.c | 1165 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1826 .fsp_cfg = ddr_fsp0_2d_cfg,
1827 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/phytec/phycore_imx8mp/ |
| H A D | lpddr4_timing.c | 1173 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1823 .fsp_cfg = ddr_fsp0_2d_cfg,
1824 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/toradex/verdin-imx8mm/ |
| H A D | lpddr4_timing.c | 1168 struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1829 .fsp_cfg = ddr_fsp0_2d_cfg,
1830 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/data_modul/imx8mp_edm_sbc/ |
| H A D | lpddr4_timing_4G_32.c | 1196 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1846 .fsp_cfg = ddr_fsp0_2d_cfg,
1847 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|
| /u-boot/board/dhelectronics/dh_imx8mp/ |
| H A D | lpddr4_timing_2G_32.c | 1187 static struct dram_cfg_param ddr_fsp0_2d_cfg[] = { variable in typeref:struct:dram_cfg_param
1837 .fsp_cfg = ddr_fsp0_2d_cfg,
1838 .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg),
|