| /u-boot/board/variscite/imx8mn_var_som/ |
| H A D | ddr4_timing.c | 13 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
519 .ddrc_cfg = ddr_ddrc_cfg,
520 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/freescale/imx8mn_evk/ |
| H A D | ddr4_timing_ld.c | 14 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1045 .ddrc_cfg = ddr_ddrc_cfg,
1046 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | ddr4_timing.c | 13 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1043 .ddrc_cfg = ddr_ddrc_cfg,
1044 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | lpddr4_timing.c | 12 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1576 .ddrc_cfg = ddr_ddrc_cfg,
1577 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | lpddr4_timing_ld.c | 13 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1429 .ddrc_cfg = ddr_ddrc_cfg,
1430 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/bsh/imx8mn_smm_s2/ |
| H A D | ddr3l_timing_256m.c | 16 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
933 .ddrc_cfg = ddr_ddrc_cfg,
934 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | ddr3l_timing_512m.c | 16 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
932 .ddrc_cfg = ddr_ddrc_cfg,
933 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/toradex/verdin-imx8mp/ |
| H A D | lpddr4_timing.c | 44 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1867 .ddrc_cfg = ddr_ddrc_cfg,
1868 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
1893 apply_cfg_patch(ddr_ddrc_cfg, ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/google/imx8mq_phanbell/ |
| H A D | lpddr4_timing_1g.c | 12 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1720 .ddrc_cfg = ddr_ddrc_cfg,
1721 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/beacon/imx8mn/ |
| H A D | lpddr4_2g_timing.c | 12 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1429 .ddrc_cfg = ddr_ddrc_cfg,
1430 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | lpddr4_timing.c | 9 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1422 .ddrc_cfg = ddr_ddrc_cfg,
1423 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/freescale/imx8mm_evk/ |
| H A D | lpddr4_timing.c | 11 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1837 .ddrc_cfg = ddr_ddrc_cfg,
1838 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/kontron/pitx_imx8m/ |
| H A D | lpddr4_timing_2gb.c | 7 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1841 .ddrc_cfg = ddr_ddrc_cfg,
1842 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | lpddr4_timing_4gb.c | 7 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1841 .ddrc_cfg = ddr_ddrc_cfg,
1842 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/advantech/imx8mp_rsb3720a1/ |
| H A D | lpddr4_timing_rsb3720a1_4G.c | 9 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1836 .ddrc_cfg = ddr_ddrc_cfg,
1837 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | lpddr4_timing_rsb3720a1_6G.c | 9 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1849 .ddrc_cfg = ddr_ddrc_cfg,
1850 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/data_modul/imx8mm_edm_sbc/ |
| H A D | lpddr4_timing_2G_32.c | 13 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1835 .ddrc_cfg = ddr_ddrc_cfg,
1836 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| H A D | lpddr4_timing_4G_32.c | 13 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1835 .ddrc_cfg = ddr_ddrc_cfg,
1836 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/engicam/imx8mp/ |
| H A D | lpddr4_timing.c | 16 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1839 .ddrc_cfg = ddr_ddrc_cfg,
1840 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/msc/sm2s_imx8mp/ |
| H A D | lpddr4_timing.c | 9 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1831 .ddrc_cfg = ddr_ddrc_cfg,
1832 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/cloos/imx8mm_phg/ |
| H A D | lpddr4_timing.c | 14 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1835 .ddrc_cfg = ddr_ddrc_cfg,
1836 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/freescale/imx93_evk/ |
| H A D | lpddr4x_timing_ld.c | 14 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1485 .ddrc_cfg = ddr_ddrc_cfg,
1486 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/phytec/phycore_imx8mm/ |
| H A D | lpddr4_timing.c | 12 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1833 .ddrc_cfg = ddr_ddrc_cfg,
1834 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/phytec/phycore_imx8mp/ |
| H A D | lpddr4_timing.c | 11 static struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1830 .ddrc_cfg = ddr_ddrc_cfg,
1831 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
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| /u-boot/board/toradex/verdin-imx8mm/ |
| H A D | lpddr4_timing.c | 14 struct dram_cfg_param ddr_ddrc_cfg[] = { variable in typeref:struct:dram_cfg_param
1836 .ddrc_cfg = ddr_ddrc_cfg,
1837 .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg),
|